[d2n-analysis-talk] BB trigger timing

[Brad Sawatzky]

On Mon, 29 Mar 2010, posik at jlab.org wrote:

>   So I am going over the trigger diagrams at
> 
> https://hallaweb.jlab.org/wiki/index.php/DAQ_Diagrams
> 
> I guess my first question is with the first trigger diagram, the one
> titled "Trigger Timing at the BigBite Weldment"
> 
> What is the Big Bite weldment? Is this the spot where the T1 is
> actually formed, meaning that TDC shower sums generated a T1?

The T1, T2, and T6 were all formed in the "Front-end trigger
electronics" racks described lower down on that page.  They were then
sent over to the Weldment which sat near the computers on the beam-left
side of the hall behind the green blocks.  The weldment housed the
trigger supervisor (TS) and DAQ hardware (ADCs, TDCs, scalers, etc).

The "Trigger timing at the BigBite Weldment for E06014" shows how the
triggers arriving the weldment were manipulated before being plugged
into the TS.

> I have written some things over the image of the trigger diagrams that
> I am looking at. For the first diagram refer to trigger_dia_1.png.
> 
>  Taking now T1 as an example I see that there is a time on the arrow
>  after the T1 trigger, I assume that this is just the time delay that
>  the wire introduces to the T1 for the first wire (154 ns). It then
>  goes to PS707, which I think is discriminator. 

Both correct.  The discriminator is just used to clean up the logic
pulse after it has passed through the long delay -- that smears out the
pulse.

>  Then a PS754. I have a list of the different components used and it
>  says that this is a Quad Logic. I Do not know what this is, but there
>  is two outputs from this unit. 

It's just used as a logic fan-out here.

>  One goes into forming the T5 and the other goes to NIM-ECL LT.  Could
>  the PS707 be acting as a sort of splitter? I also do not know what
>  the NIM-ECL LT does.

LT = level translator.  It converts from NIM standard (used with coax
cables like RG-58) to ECL (used with twisted-pair).

>  So if I add up the timing of the wires, then does that mean that the
>  T1 reaches the Trigger supervisor 174 ns ? Also I was wondering if

Sort of.  You also have to add on roughly 10ns per module.  Even then,
you have to ask 174ns relative to what?  There should be (I hope) a
timing diagram like the one in the dotted box that shows relative timing
of the triggers arriving at the TS for an electron (or pulser) event...
The 'trigger timing' diagram is really more of a logic block layout
(unfortunately).

>  you knew the resolution of the Big Bite TDCs (1881's). Looking at the
>  scintillator db files, I seen 35ps/chan, however I do not know how
>  correct this is.

The 1881s are ADCs.  The 1877s are TDCs, and have a resolution of
0.5ns/bin.

> Now the second trigger diagram at
> https://hallaweb.jlab.org/wiki/index.php/DAQ_Diagrams
> 
> titled "Re-timing at the Big Bite Weldment" deals with the L1A from
> the trigger supervisor and re-times it. For this part I will refer to
> trigger_dia_2.png. We have our L1A which goes to ECL-NIM LT unit and
> then to the PS754. The signal is then split to a LC222 and a PS754. I
> think the LC222 is a gate delay generator, and is responsible for
> forming a large L1A gate? The large L1A gate is then compared to the
> T6 gate and this is what is responsible for forming the re-timed L1A?

The intent of the retiming was to help make sure that, whenever
possible, the ADCs and TDCs were triggered by a signal timed off the
shower detector (ie. the T6).  This helped keep the ADC gate timing
consistent and kept the T6 trigger timing the same as the T2 trigger
timing (rather than having one timed off the shower and the other timed
off the Cerenkov).

> There are three inputs listed in a dotted box below this "Re-timing at
> the Big Bite Weldment" diagram and I was wondering if how I have them
> labeled in red in the trigger_dia_2.png image is correct?

The PS794 on the right was used to suppress multiple pulses from being
send to the ADCs/TDCs.  The discriminators here are all operating on
logic signals -- their real function was to either fan-out a signal, or
modify the width of a pulse.  One P754 block has (1/4) in it and the
other has (2/4).  The latter means it requires an overlap on 2 of its
inputs.  The former means it requires an 'overlap' of 1 -- ie. it just
fans out the single input.

The timing in the dotted box are the three inputs to the PS754(2/4)
block.  The output of that module will carry the timing of the T6, but
only if the L1A is present.  The 2nd copy guarantees that we still
trigger the modules for non-T6 events by forcing a L1A and delayed-L1A
overlap at the end.

-- Brad

-- 
Brad Sawatzky, PhD <brads at jlab.org>  -<>-  Jefferson Lab / Hall C / C111
Ph: 757-269-5947  -<>-  Fax: 757-269-5235  -<>- Pager: brads-page at jlab.org
The most exciting phrase to hear in science, the one that heralds new
  discoveries, is not "Eureka!" but "That's funny..."   -- Isaac Asimov