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Yes these changes will be needed but most of them are "paper" changes now and no drawings or HIM layouts are completed yet. No hardware or wiring has been done to date and now is the time to incorporate mods.<br>
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Changes are expected and evolution of the HMI screens never stops. One only has to wait until the experimenters have to use the screens and demand changes.<br>
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By using differential current mode for the LVDT eliminates the need for 10 dataforth signal conditioners and separates the strains gauges from the LVDTs so they are not tied to each other via the IF16 modules on the rst timing of the module. Allows for more
flexibility in noise reduction and filtering options.</div>
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The HMS uses signal ended voltages for the LVDT and the SHMS uses different current mode. Both work well in that regard. LVDTs can become noisy due to hardware and other factors and this leads to excessive valve wear. So isolating all the LVDT and motor relays
to one area may be better. <br>
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Other hardware may be added to the PLC controls as the project moves along, such as magnetic field devices for test lab use only.
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Hope this doesn't cause too much grief.</div>
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Cheers</div>
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Steven<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Pablo Campero Rojas <campero@jlab.org><br>
<b>Sent:</b> Thursday, April 30, 2020 11:02 AM<br>
<b>To:</b> Steven Lassiter <lassiter@jlab.org>; dsg-halla_magnets@jlab.org <dsg-halla_magnets@jlab.org>; Whit Seay <wseay@jlab.org><br>
<b>Subject:</b> Re: [Dsg-halla_magnets] I/O rack layout</font>
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<span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">Based on this new proposed disposition of the PLC layout, I can see the following changes involved:</span></div>
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<li><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">Channel assigned in the PLC code for the CCR JT valves, temperature sensors, vacuum, LL, and pressure transducers.</span></li></ul>
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<li><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">Drawings:</span><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal"> A00000-16-03-1150</span><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">,
A00000-16-03-0450</span><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal"> sheet 3,6,9 and 12</span><br>
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<a href="https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-1150-1.pdf" id="LPlnk667523"><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-1150-1.pdf</span></a></div>
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<a href="https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-0450-3.pdf" id="LPlnk187477"><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-0450-3.pdf</span></a><br>
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<li><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">Changing the LVDTs signal readout from "single ended mode" to "differential mode" (1756-IF16 adc module modes) involved the addition of one extra adc module, since
only 8 channels from the total 16 can be used.</span></li><li><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">Readout signals for heat exchanger's LVDTs were moved to a new ADC module.</span></li></ul>
<div><span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt; line-height:normal">So far this is what I noticed, and will need to be changed if we want to follow the proposed layout.</span></div>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Dsg-halla_magnets <dsg-halla_magnets-bounces@jlab.org> on behalf of Steven Lassiter <lassiter@jlab.org><br>
<b>Sent:</b> Thursday, April 30, 2020 10:02 AM<br>
<b>To:</b> dsg-halla_magnets@jlab.org <dsg-halla_magnets@jlab.org>; Whit Seay <wseay@jlab.org><br>
<b>Subject:</b> [Dsg-halla_magnets] I/O rack layout</font>
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Hello All,</div>
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I propose the following changes to the CLEO-II I/O rack layout.</div>
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Lays out common components in a more logical order.</div>
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Steven<br>
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