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<span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">Based on this new proposed disposition of the PLC layout, I can see the following changes involved:</span></div>
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<li><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">Channel assigned in the PLC code for the CCR JT valves, temperature sensors, vacuum, LL, and pressure transducers.</span></li></ul>
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<li><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">Drawings:</span><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;"> A00000-16-03-1150</span><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">,
A00000-16-03-0450</span><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;"> sheet 3,6,9 and 12</span><br>
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<a href="https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-1150-1.pdf" id="LPlnk667523"><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-1150-1.pdf</span></a></div>
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<a href="https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-0450-3.pdf" id="LPlnk187477"><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">https://www.jlab.org/div_dept/physics_division/dsg/technical_documentation/Hall_A/SoLID/A00000-16-03-0450-3.pdf</span></a><br>
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<li><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">Changing the LVDTs signal readout from "single ended mode" to "differential mode" (1756-IF16 adc module modes) involved the addition of one extra adc module,
since only 8 channels from the total 16 can be used.</span></li><li><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">Readout signals for heat exchanger's LVDTs were moved to a new ADC module.</span></li></ul>
<div><span style="font-family: Calibri, Helvetica, sans-serif; font-size: 11pt; line-height: normal;">So far this is what I noticed, and will need to be changed if we want to follow the proposed layout.</span></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Dsg-halla_magnets <dsg-halla_magnets-bounces@jlab.org> on behalf of Steven Lassiter <lassiter@jlab.org><br>
<b>Sent:</b> Thursday, April 30, 2020 10:02 AM<br>
<b>To:</b> dsg-halla_magnets@jlab.org <dsg-halla_magnets@jlab.org>; Whit Seay <wseay@jlab.org><br>
<b>Subject:</b> [Dsg-halla_magnets] I/O rack layout</font>
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Hello All,</div>
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I propose the following changes to the CLEO-II I/O rack layout.</div>
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Lays out common components in a more logical order.</div>
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Steven<br>
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