[Dsg-hallb_magnets] Applying digital filter to Torus Fast-Daq

[Tyler Lemon]

Hello Ruben, 

I have been investigating the task of applying a digital filter to the Hall B Magnets Fast-Daq and have the following questions: 


    1. How should filtering methods and options be tested? It was mentioned that it should be tested off-line; could you clarify on what "tested off-line" means? 
    2. What is the deadline for this task? There are two different dates for the deadline in two emails below. The first email from January 5 is in blue; second email from January 6 in green. 

Please let me know. 

Best regards, 
Tyler 

Sent: Thursday, January 5, 2017 12:45:14 PM 
Subject: Torus - noisy iso-amps 

Hi Tyler, 

Could you sort out the digital filtering for the Torus first and then do the same for the solenoid? 

We are intending to energize the Torus again on 02nd or 03rd Feb so could you aim to have your filtering implemented and tested off-line (with help from Probir, Nick and Pablo) by 01.31.2017 ? 

Regards 

Ruben 


Sent: Friday, January 6, 2017 9:19:55 AM 
Subject: I and C Related Torus Punch List Items 

Gentlemen, 

Please ensure that all the following I and C related Torus Punch List items are completed by 16th Jan 2017 unless otherwise stated. 

There are other punch list items which Dave and I are progressing separately. 

1. Implement a lead flow solenoid vent through SV8122 (2 minutes) upon high return pressure with insufficient reduced lead flow (Alarm/warming should activate), cable needed 
Please work with Scot Spiegel to define and fabricate the cable. (Nick, Dave, Scot) 

2. Check all of lead flow controllers/lead heaters and TD121A/B temperature sensors AND be sure they are consistent with Voltage taps on same leads 
Work with Probir to do this. (Nick, Probir) 

3. Complete all electrical wiring diagrams and submit to the system for approval (Scot) 

4. Implement and test digital filtering within cRIO FPGA to reduce iso-amp noise (Tyler, Nick, Probir) 
Tyler - Nick suggested that it might also be an idea to move all the scaling calcs (and perhaps unit conversion calcs) to the FPGA to reduce the load on the cRIO processor? 
See if it makes sense to do that. 
You and Probir will need to run tests of course to ensure all the scaling is still correct. 
And if the noise level has truly been reduced, then Probir and Nick will need to reassess the voltage threshold limits that we are currently using. 

5. Automate warning beacons (Krister) - by 27th Jan 

6. Check that the three temperature sensors (PT100s) on the relief valves on the TST are cabled up, cables are routed to terminal blocks and LV chassis (or Cryocon), LabVIEW (if via the LV chassis) has been updated, PLC code has been updated and these sensors are displayed on the EPICS helium screen. (Probir / Nick/ Wesley) 

7. Update alarm handler to use the on-call cell phone no. provided by Doug, 757 748 5048 Sprint (Wesley) 

8. Mount and wire up remaining three PT100 sensors to the relief valves on the magnet. Ensure the cables are labeled correctly. (Krister) - by 27th Jan 

9. Remove requirement for controlled ramp down of magnet on ESR 'fail' signal (Nick) 


Regards 

Ruben 

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