[Dsg-hallb_magnets] Sept 2017 QD delay test analysis

[Pablo Campero]

Hi, 

Since during the last Solenoid trip on 09/29/2018 was sensed only by QD1:Ch1 (Hardware unit) and the FastDAQ data did not showed any voltage spikes that could generated the fast dump, this could be an indicator that certainly QD's units are sensing voltage signals/Noise that are not been showed on the FastDAQ data recorded. We know that the VTs voltage signals in both cases are get on two different ways: 

QD Path : Solenoid magnet > Resistor Box > VT panel (can be jumpered out) > QD unit input 
FastDAQ data Path : Solenoid magnet > Resistor Box > VT panel > ISO/Voltage Trans. P29000 >cRIO FPGA filter> FastDAQ voltage tap data record. 

Maybe, can we think that would be worth to re-check the Resistor box and the possibility of the addition of a hardware filter right in front of the QDs? 

Regards, 
Pablo 

From: "Tyler Lemon" <tlemon at jlab.org> 
To: "dsg-hallb magnets" <dsg-hallb_magnets at jlab.org> 
Sent: Monday, October 8, 2018 3:58:46 PM 
Subject: [Dsg-hallb_magnets] Sept 2017 QD delay test analysis 

Hello, 

Since there have been more QD problems lately with the Hall B Solenoid, DSG has started to re-look at data from the QD tests Brian performed back in September 2017 (original results at https://logbooks.jlab.org/entry/3485488). The one caveat with this new analysis, though, is that the results apply only to the QD board tested. The ones actually in use in the hall may behave differently. 

For Brian's test, he mentions that all channels were noted to have 100 mV trip thresholds. From the previous test's data, we created a new spreadsheet (attached). In the spreadsheet, each QD delay setting tested is denoted by the color of the columns. The columns with the title "Never Tripped" indicate conditions used where the QD channels never tripped. Columns titled "Always Tripped" indicate conditions used when the QD channels always tripped. It wasn't explicitly said in the original logbook data, but we assumed that between the pulse widths for "Always Tripped" and "Never Tripped" there were pulse widths where only some of the pulses tripped the QD channels. 

The first row of plots is Brian's original plots reformatted with the colors used in the spreadsheet for the QD delay times. 

The extra analysis performed is to see the QD trips during the test in relation to the charge of the input pulse. The charge (integral of current over time) of the pulse is proportional to the integral of voltage over time by a factor determined by the impedance of the circuit and instrumentation (since the impedance is unknown, we were only able to calculate the proportional voltage-over-time integral). The charge-pulse amplitude relationship is shown in the second and third rows of plots. 

>From this data, it seems that the QD delay is really increasing the total charge needed to trip the channels. It also seems that a voltage spike that is large in amplitude and low in duration may still trip the QDs. 

>From Probir's slides last Friday, there was a ~400 mV pulse that lasted 1.1 ms on VT19. Could that have caused the amplitude of the pulse gave it enough of a charge to trip the QD? 

Best regards, 
Tyler 


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