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<p>Hi Tyler,</p>
<p>all the schematics are located on the M drive at the following
location</p>
<p>M:\ees\RF\Bachimanchi\Torus_Instrumentation\LV_Chassis_New\Schematics</p>
<p>FPGA code is located on the M drive at the following location</p>
<p>M:\ees\RF\Bachimanchi\Torus_Instrumentation\LV_Chassis_New\LV_Chassis_New_FPGA_RS232_Uploaded_In_The_HallB</p>
<p>please let me know, if you have any questions or need more
information</p>
<p>Thanks,</p>
<p>Rama<br>
</p>
<br>
<div class="moz-cite-prefix">On 12/7/2016 2:53 PM, Tyler Lemon
wrote:<br>
</div>
<blockquote
cite="mid:1369272920.4522187.1481140426284.JavaMail.zimbra@jlab.org"
type="cite">
<div style="font-family: times new roman,new york,times,serif;
font-size: 12pt; color: #000000">
<div>Hello Rama,<br>
</div>
<div><br data-mce-bogus="1">
</div>
<div>Could you send the FPGA code and schematic for the LV
excitation chassis? We cannot find it on the M Drive. DSG
would need both to be able to provide long term support on the
LV excitation cRIO system.<br data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>Best regards,<br data-mce-bogus="1">
</div>
<div>Tyler<br data-mce-bogus="1">
</div>
<div><br>
</div>
<div><br data-mce-bogus="1">
</div>
<div><span data-mce-style="color: #0000ff;" style="color: rgb(0,
0, 255);"><b>From: </b>"Renuka Rajput-Ghoshal"
<a class="moz-txt-link-rfc2396E" href="mailto:renuka@jlab.org"><renuka@jlab.org></a></span><br>
</div>
<div data-marker="__HEADERS__"><span data-mce-style="color:
#0000ff;" style="color: rgb(0, 0, 255);"><b>To: </b>"Ramakrishna
Bachimanchi" <a class="moz-txt-link-rfc2396E" href="mailto:bachiman@jlab.org"><bachiman@jlab.org></a></span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);"><b>Cc: </b>"Tyler Lemon" <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a>,
"Ruben Fair" <a class="moz-txt-link-rfc2396E" href="mailto:rfair@jlab.org"><rfair@jlab.org></a></span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);"><b>Sent: </b>Thursday, December 1, 2016 2:38:45 PM</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);"><b>Subject: </b>Fwd: [Dsg-hallb_magnets] LV
excitation chassis FPGA</span><br>
</div>
<div><br>
</div>
<div data-marker="__QUOTED_TEXT__"><span data-mce-style="color:
#0000ff;" style="color: rgb(0, 0, 255);">Hello Rama,</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Could you please answer Tyler.</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Thanks</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Renuka</span><br>
<br>
<br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">----- Forwarded Message -----</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">From: "Tyler Lemon" <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a></span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">To: "dsg-hallb magnets"
<a class="moz-txt-link-rfc2396E" href="mailto:dsg-hallb_magnets@jlab.org"><dsg-hallb_magnets@jlab.org></a></span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Sent: Thursday, December 1, 2016 2:33:01 PM</span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Subject: [Dsg-hallb_magnets] LV excitation chassis
FPGA</span><br>
<br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Dear Renuka and Ruben, </span><br>
<br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">We cannot find the LV excitation chassis FPGA code
for the Hall B Magnets on the M Drive. Could you send the
FPGA and also the schematic for the LV excitation chassis? </span><br>
<br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Best regards, </span><br>
<span data-mce-style="color: #0000ff;" style="color: rgb(0, 0,
255);">Tyler </span><br>
<br>
</div>
</div>
</blockquote>
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