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<div>Hi Brian</div>
<div dir="ltr">Please increase the threshold sum of voltages on slices only (in and out lead) not coils or splices between coils by another 25 mV (presently been set to 80 mV) to change to 105 mV. This is on PLC side software limits not on the hardware trip
threshold…</div>
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<div dir="ltr">Regards </div>
<div dir="ltr">Probir </div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Dsg-hallb_magnets <dsg-hallb_magnets-bounces@jlab.org> on behalf of beng--- via Dsg-hallb_magnets <dsg-hallb_magnets@jlab.org><br>
<b>Sent:</b> Tuesday, October 18, 2022 10:25:02 AM<br>
<b>To:</b> dsg-hallb_magnets@jlab.org <dsg-hallb_magnets@jlab.org><br>
<b>Subject:</b> [Dsg-hallb_magnets] [New Logentry] Solenoid Controlled Ramp</font>
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<h1 class="x_node-title"><a href="https://logbooks.jlab.org/entry/4062189" rel="bookmark">Solenoid Controlled Ramp</a>
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<p class="x_author-datetime">Lognumber <a href="https://logbooks.jlab.org/entry/4062189" class="x_lognumber" data-lognumber="4062189">
4062189</a>. Submitted by <a href="https://logbooks.jlab.org/user/beng">beng</a> on
<time datetime="2022-10-18T10:20:08-0400"><a href="https://logbooks.jlab.org/entries?start_date=1666099208&end_date=1666106408&book=DSGLOG&book=HBSOLENOID">Tue, 10/18/2022 - 10:20</a></time>.
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<th>Logbooks: </th>
<td><a href="https://logbooks.jlab.org/book/dsglog">DSGLOG</a> <a href="https://logbooks.jlab.org/book/hbsolenoid">
HBSOLENOID</a></td>
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<p>According to the PLC it was COMP4 that was the cause of the controlled ramp.</p>
<p>Looking at the VT data nothing stands out as being bad.</p>
<p>Found that the dead-band for the some of the comparators is probably set to low as looking at the archived data doesn't show anything. The threshold for COMP4 is 0.08 and the dead-band is 0.05 as an example.</p>
<p>Various plots are attached.</p>
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<div class="x_image-wrapper"><img class="x_image-style-plentybig" src="https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-mya-interlock.png" width="960" height="510" alt="" title="MyaPlot - Interlocks"></div>
<div class="x_image-wrapper"><img class="x_image-style-plentybig" src="https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-mya.png" width="960" height="510" alt="" title="MyaPlot - Comparators"></div>
<div class="x_image-wrapper"><img class="x_image-style-plentybig" src="https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-interlocks.PNG" width="960" height="657" alt="" title="PLC Interlocks"></div>
<div class="x_image-wrapper"><img class="x_image-style-plentybig" src="https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-soft_quench.PNG" width="960" height="657" alt="" title="PLC Software Quench - COMP4 bad"></div>
<div class="x_image-wrapper"><img class="x_image-style-plentybig" src="https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-vt.png" width="960" height="612" alt="" title="VTs related to COMP4"></div>
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