<html><body><div style="font-family: arial,helvetica,sans-serif; font-size: 12pt; color: #000000"><div>Dear Tyler,</div><div>Thank you very much for the detailed clarification of the cRio-based slow control design.</div><div>I completely agree with what you wrote in items 1) and 2) of your note.</div><div>My main concern was about the integration of the RICH cRio to the existing CLAS12 slow control system.</div><div>I am happy that you are going to coordinate with Nathan to make sure that both systems will interact correctly in the future.</div><div>Thanks,</div><div>Valery</div><div><br data-mce-bogus="1"></div><div><br></div><hr id="zwchr" data-marker="__DIVIDER__"><div data-marker="__HEADERS__"><blockquote style="border-left:2px solid #1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;" data-mce-style="border-left: 2px solid #1010FF; margin-left: 5px; padding-left: 5px; color: #000; font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Tyler Lemon" <tlemon@jlab.org><br><b>To: </b>"dsg-rich" <dsg-rich@jlab.org><br><b>Sent: </b>Tuesday, March 14, 2017 8:37:51 AM<br><b>Subject: </b>[Dsg-rich] RICH slow controls and hardware interlock clarifications<br></blockquote></div><div data-marker="__QUOTED_TEXT__"><blockquote style="border-left:2px solid #1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;" data-mce-style="border-left: 2px solid #1010FF; margin-left: 5px; padding-left: 5px; color: #000; font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000" data-mce-style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000;"><div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000" data-mce-style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000;"><div><div>Hello Valery, <br></div><br><div>After our conversation yesterday, I wanted to make sure to clarify a few things we talked about.</div><br><div>1.) The RICH Hardware Interlock system DSG has been developing is a cRIO-based system that uses LabVIEW. The RICH Hardware Interlock System is modeled after the hardware interlock systems for the SVT and Forward Tagger, so the RICH system will not be unique in Hall B.</div><br><div>2.) The advantage of having this cRIO-based system is that it is not dependent on any network connection. If for some reason, the network and EPICS goes down, the cRIO ensures that RICH can still be operated or turned off safely.<br></div><br><div>3.) cRIO has built-in functionality to act as an EPICS server or EPICS client. Once DSG has finished the LabVIEW program, we will coordinate with Nathan to make sure the necessary information is passed to EPICS.</div><br><div>4.) The LabVIEW GUI on slide 17 of the presentation shared last week (slide attached) is for the Gas System cRIO. It does not replace any existing EPICS screens. It will only be seen if one goes to the cRIO touchscreens in Hall B Gas Shed or on the Forward Carriage.</div><br><div>5.) The RICH Hardware Interlock system has been in development since May 2016. The email below from May 3, 2016 is the first mention in email of it. The air cooling system diagrams created by George in May 2016 also show the RICH Hardware Interlock System cRIO. All major components (cRIO chassis, cRIO modules, temperature sensors, humidity sensors, etc.) were procured in Summer 2016.<br></div><br><div>Please let us know if you have any other questions or if anything is unclear.<br></div><br><div>Best regards,<br></div><div>Tyler<br></div><br></div><br><div><span style="background-color: rgb(255, 255, 0);" data-mce-style="background-color: #ffff00;"><strong><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">From: "Tyler Lemon" <tlemon@jlab.org></span></strong></span><br></div><div><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;"><b>To: </b>"clas12 rich" <clas12_rich@jlab.org></span><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;"><b>Cc: </b>"Patrizia Rossi" <rossi@jlab.org></span><br><span style="background-color: rgb(255, 255, 0);" data-mce-style="background-color: #ffff00;"><strong><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Sent: Tuesday, May 3, 2016 1:09:45 PM</span></strong></span><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;"><b>Subject: </b>[Clas12_rich] RICH cooling, interlocks and assembly structure</span><br></div><br><div><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Dear Marco Mirazita,</span><br><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">We held a short meeting among DSG members to discuss RICH gas and cooling system, interlock system, and anchoring the assembly structure. We discussed the following:</span><br><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Gas and Air Compressor Cooling System:</span><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">George will create a scheme for the air compressor cooling and send it to Saptarshi Mandal and Ron Bartek for ASME approval. We will also compile a list of components to be purchased (e.g. compressors, tanks, fittings) and the price quote for each component. </span><br><br><span style="background-color: rgb(255, 255, 0);" data-mce-style="background-color: #ffff00;"><strong><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Interlock System:</span></strong></span><br><span style="background-color: rgb(255, 255, 0);" data-mce-style="background-color: #ffff00;"><strong><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">We have received Valery’s suggestions on the interlock system and as in my previous email, please let us know of any other interlocks would be required. For the hardware interlocks, we will develop a cRIO-based system identical to the SVT interlock system that Peter developed. There will also be software interlocks for alarm handling and controls in EPICS. We will compile a list of all components to be purchased (e.g. cRIO system, monitoring sensors) and the price quote for each component.</span></strong></span><br><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Assembly Structure:</span><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">To anchor the assembly structure in EEL 124, George informed us that we will be able to drill holes and anchor the structure to the floor. What size bolts would be used to anchor the structure? Also, is there an engineering drawing for the assembly structure that specifies the lift points for the structure and the bolt size? Please let us know. The drawing would need to be reviewed by Hall B Engineering because of the bolt size and each lift will be an engineered list.</span><br><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Please let us know about the engineering drawings and where we could find them. Thank you in advance.</span><br><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Best Regards,</span><br><span style="color: rgb(0, 0, 255);" data-mce-style="color: #0000ff;">Tyler</span></div></div><br></div></div><br>_______________________________________________<br>Dsg-rich mailing list<br>Dsg-rich@jlab.org<br>https://mailman.jlab.org/mailman/listinfo/dsg-rich<br></blockquote></div></div></body></html>