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<p>Hi Valery,</p>
<p>We have received the CAEN HV modules and a few of the LV modules.</p>
<p>The new CAEN mainframe will be delivered this week.(hopefully).</p>
We will fabricate a LV cable set including the sense line that will
ultimately be used in the Hall. This cable set will provide<br>
LV power for thirty-two(32) 'tiles' and will be the length
determined by Bob Miller. <br>
<br>
As soon as we receive the mainframe, we can move it to the EEL clean
room for initial testing. How does the cRIO hardware interlock
system<br>
connect/control the HV, LV modules? Is it simply a closure to the
CAEN mainframe CPU module(A4528) front panel interlock input? <br>
<br>
-Chris<br>
~~~~~~~~~~~~~~~~~~ <br>
<br>
<div class="moz-cite-prefix">On 7/31/2017 10:47 AM, Valery
Kubarovsky wrote:<br>
</div>
<blockquote type="cite"
cite="mid:895633627.1619194.1501512442241.JavaMail.zimbra@jlab.org">
<div style="font-family: arial,helvetica,sans-serif; font-size:
12pt; color: #000000">
<div>Chris,</div>
<div>DSG wants to test RICH HV and LV interlock.</div>
<div>Could we install everything that we have in the EEL
building clean room?</div>
<div>Regards,</div>
<div>Valery</div>
<div><br data-mce-bogus="1">
</div>
<hr id="zwchr" data-marker="__DIVIDER__">
<div data-marker="__HEADERS__"><b>From: </b>"Tyler Lemon"
<a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
<b>To: </b>"dsg-rich" <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
<b>Sent: </b>Monday, July 31, 2017 8:17:07 AM<br>
<b>Subject: </b>[Dsg-rich] RICH HV/LV board interlock testing<br>
</div>
<div><br>
</div>
<div data-marker="__QUOTED_TEXT__">
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<div>
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<div>
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<div style="font-family: times new roman,new
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<div style="font-family: times new roman,new
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#000000" data-mce-style="font-family: times
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12pt; color: #000000;">
<div>Hello Valery,<br>
</div>
<br>
<div>We need to test the interlock enable
ability of RICH HV and LV boards to be
able to fully complete the cRIO-based
hardware interlock system. <br>
</div>
</div>
<div style="font-family: times new roman,new
york,times,serif; font-size: 12pt; color:
#000000" data-mce-style="font-family: times
new roman,new york,times,serif; font-size:
12pt; color: #000000;"><br>
</div>
<div style="font-family: times new roman,new
york,times,serif; font-size: 12pt; color:
#000000" data-mce-style="font-family: times
new roman,new york,times,serif; font-size:
12pt; color: #000000;">Marco Contalbrigo
mentioned that the power supplies would be
moved soon to start installing the
electronics on the electronic panel.<br>
<br>
<div>Could we install all HV and LV boards
in the power supply mainframe to be able
to test the interlock enable functions?<br>
</div>
<br>
<div>Best regards,<br>
</div>
<div>Tyler</div>
</div>
</div>
</div>
</div>
</div>
</div>
</div>
<br>
</div>
</div>
<br>
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