<html><body><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div data-marker="__QUOTED_TEXT__"><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><div><span style="color: rgb(0, 0, 255);">Hello Chris,</span><br></div><br><div><span style="color: rgb(0, 0, 255);">My reply is inline below in blue.</span><br></div><br><br><div>Hi,<br><br>If the 'hardware interlock system' produces an interlock relay closure, and this closure is the logical OR of several signals, then the closure should be connected to the CAEN mainframe interlock input(CPU). Is this the case?</div><br><div><span style="color: rgb(0, 0, 255);">For the LV boards, the hardware interlock system will open a relay to break the short circuits required at the service connector to enable a group's output. This is described in on page 7 of the attached manual for the A2518 boards.</span><br></div><div><span style="color: rgb(0, 0, 255);"><br></span></div><div><span style="color: rgb(0, 0, 255);">We are not using the interlock input on the CAEN mainframe because when asked, Valery said HV should be turned off before LV. Using the interlock input on the mainframe will shutoff both HV and LV at the same time.<br></span></div><div><span style="color: rgb(0, 0, 255);"><br></span></div><br><div><br>The interlock signals on the A2518 boards control two groups of 4 low voltage outputs. Each output channel has over-voltage and over-current trip points, <br></div></div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><br></div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><span style="color: rgb(0, 0, 255);"><span style="color: rgb(0, 0, 255);">We are not monitoring any current or voltage output of HV or LV.</span> The hardware interlock system will only disable HV/LV in the event that one of the hardware interlock system sensors (temperature, humidity, N2 flow, cooling airflow, cooling tank pressure) goes out of the determined limits. <br></span></div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><br></div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000">and I do not see the need to interface to each group of LV interlocks if there is a global interlock signal that will latch a disable condition.</div><div style="font-family: times new roman,new york,times,serif; font-size: 12pt; color: #000000"><br><div><span style="color: rgb(0, 0, 255);">We have programed the hardware interlock system in a way that disables all LV groups at once and all HV channels at once. The hardware interlock system does not disable/enable each individual group.<br></span></div><br><br><div><strong><span style="color: rgb(0, 0, 255);">Is it really necessary to sequence the shutoff of HV and LV? </span></strong></div><div><strong><span style="color: rgb(0, 0, 255);">If not, we can change the hardware interlock system code to use the CAEN mainframe interlock input.</span></strong></div><div><span style="color: rgb(0, 0, 255);"><br></span></div><div><span style="color: rgb(0, 0, 255);">Best regards,<br></span></div><div><span style="color: rgb(0, 0, 255);">Tyler</span></div></div></div></div></div></div></div></div></div></div><br></div></div></body></html>