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Hi All,<br>
<br>
The RICH air cooling supply still needs to be properly configured to
supply 2 RICH detectors. I have attached the testing and setup
procedure I wrote up to this email.<br>
<br>
Cheers,<br>
George<br>
<br>
<div class="moz-cite-prefix">On 9/5/2018 2:42 PM, Tyler Lemon wrote:<br>
</div>
<blockquote type="cite"
cite="mid:476325904.316874.1536172937868.JavaMail.zimbra@jlab.org">
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font-size: 12pt; color: #000000">
<div>Hello Marco and Valery,<br data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>A few months ago, you mentioned that it'd be good to figure
out more precisely what airflow is needed to keep RICH
electronics cool.<br data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>Since there will not be beam and Hall B will be open until
next week, would we be able to run tests this week to
determine how changes in cooling airflow affect RICH FPGA
temperatures and hardware interlock RTDs?<br
data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>The general procedure in the study would be:<br
data-mce-bogus="1">
</div>
<div>1.) turn on HV/LV and let the EP reach its normal running
temperature.<br data-mce-bogus="1">
</div>
<div>2..) decrease airflow to set values (decrease in ~50 slm
increments?).<br data-mce-bogus="1">
</div>
<div>3.) Allow RICH to reach a steady temperature after change.<br
data-mce-bogus="1">
</div>
<div>4.) Repeat steps 2 and 3 until FPGA temperatures reach some
upper limit (maybe 75 deg C?)<br data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>The tests would also allow better limits on the hardware
interlock to be set because we would have data supporting at
what airflow RICH electronics temperatures start to get too
high.<br data-mce-bogus="1">
</div>
<div><br data-mce-bogus="1">
</div>
<div>Please let us know.</div>
<div><br data-mce-bogus="1">
</div>
<div>Best regards,<br data-mce-bogus="1">
</div>
<div>Tyler<br data-mce-bogus="1">
</div>
</div>
<br>
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<br>
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</blockquote>
<br>
<pre class="moz-signature" cols="72">--
George Jacobs
Jefferson Lab (TJNAF)
STE 12
12000 Jefferson Ave.
Newport News, VA 23606
(office) 757-269-7021
(cell) 757-876-0480
(email) <a class="moz-txt-link-abbreviated" href="mailto:jacobsg@jlab.org">jacobsg@jlab.org</a>
(website) <a class="moz-txt-link-freetext" href="https://userweb.jlab.org/~jacobsg">https://userweb.jlab.org/~jacobsg</a></pre>
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