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<p>Hi All,</p>
<p>The FPGAs have a firmware set point for the die temperature. Ben
can verify this set point, but it sure sounds like the 'interlock'
systems rely on software code. Are there watchdog timers set up in
case the code stops running? <br>
</p>
<p>For a true hardware interlock, one that does not depend on
software, there should be temperature probes coupled directly to a
comparator circuit which latches off the Low_Voltage outputs to
the FPGA boards. From these email threads, it sounds like all the
temperature devices are monitored with software, and if a software
set point threshold is violated, then the Low_Voltage is turned
OFF. If the monitored temperature devices go below the software
set point threshold, is the Low_Voltage power reapplied
automatically?</p>
<p>Thanks,</p>
<p>-Chris</p>
<p>~~~~~~~~~~~~~~~~~</p>
<br>
<div class="moz-cite-prefix">On 10/16/2018 9:40 AM, Valery
Kubarovsky wrote:<br>
</div>
<blockquote type="cite"
cite="mid:26066286.4049022.1539697212523.JavaMail.zimbra@jlab.org">
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<div>The detector (actually LV in this particular case, because
the HV was off at that moment)</div>
<div>was shut down by software interlock that monitors the FPGS
temperature.</div>
<div><br>
</div>
<hr id="zwchr" data-marker="__DIVIDER__">
<div data-marker="__HEADERS__">
<blockquote style="border-left:2px solid
#1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;"
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font-style: normal; text-decoration: none; font-family:
Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Marco
Mirazita" <a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
<b>To: </b>"Tyler Lemon" <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
<b>Cc: </b>"Valery Kubarovsky" <a class="moz-txt-link-rfc2396E" href="mailto:vpk@jlab.org"><vpk@jlab.org></a>,
<a class="moz-txt-link-abbreviated" href="mailto:rich@jlab.org">rich@jlab.org</a>, "dsg-rich" <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
<b>Sent: </b>Tuesday, October 16, 2018 9:37:41 AM<br>
<b>Subject: </b>Re: [Rich] [Dsg-rich] FPGA temp alarm<br>
</blockquote>
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<blockquote style="border-left:2px solid
#1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;"
data-mce-style="border-left: 2px solid #1010FF; margin-left:
5px; padding-left: 5px; color: #000; font-weight: normal;
font-style: normal; text-decoration: none; font-family:
Helvetica,Arial,sans-serif; font-size: 12pt;">But we have a
soft interlock shutting down the system if fpga <br>
temperature goes above 75 deg.<br>
<br>
<br>
Il 2018-10-16 14:24 Tyler Lemon ha scritto:<br>
> Hello Marco,<br>
> <br>
> The hardware interlock system does not monitor FPGA
temperatures. It<br>
> monitors the RTDs installed in the EP.<br>
> <br>
> The hardware interlock system did not trip off the
electronics because<br>
> the strange temperature readings were only seen on the
FPGA<br>
> temperature readouts.<br>
> <br>
> Best regards,<br>
> Tyler<br>
> <br>
> -------------------------<br>
> <br>
> FROM: "Mirazita Marco"
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> TO: "Valery Kubarovsky" <a class="moz-txt-link-rfc2396E" href="mailto:vpk@jlab.org"><vpk@jlab.org></a><br>
> CC: <a class="moz-txt-link-abbreviated" href="mailto:rich@jlab.org">rich@jlab.org</a>, "dsg-rich" <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SENT: Tuesday, October 16, 2018 8:16:06 AM<br>
> SUBJECT: Re: [Rich] [Dsg-rich] FPGA temp alarm<br>
> <br>
> Hi Valery,<br>
> thank you, in fact my main worry was that the interlock
didn't shut<br>
> down<br>
> the electronics.<br>
> It would be anyway good to understand why we had this
event.<br>
> I saw from the strip charts that also the LV currents
and voltages<br>
> have<br>
> frequent random spikes.<br>
> Marco<br>
> <br>
> Il 2018-10-16 13:55 Valery Kubarovsky ha scritto:<br>
>> Marco,<br>
>> If you take a more careful look you will find out
that the LV was<br>
> shut<br>
>> down.<br>
>> The HV was off. We investigate the reason. It is
the first time we<br>
> had<br>
>> such an event.<br>
>> Probably it was connected with the software update
that was done<br>
>> approximately at the same time.<br>
>> Regards,<br>
>> Valery<br>
>> <br>
>> -------------------------<br>
>> <br>
>>> FROM: "Marco Mirazita"
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
>>> TO: <a class="moz-txt-link-abbreviated" href="mailto:dsg-rich@jlab.org">dsg-rich@jlab.org</a>, <a class="moz-txt-link-abbreviated" href="mailto:rich@jlab.org">rich@jlab.org</a><br>
>>> SENT: Tuesday, October 16, 2018 4:03:24 AM<br>
>>> SUBJECT: [Dsg-rich] FPGA temp alarm<br>
>> <br>
>>> Hi all,<br>
>>> yesterday at about 4:20 pm jlab time I received
several alarm<br>
>>> messages<br>
>>> saying that the FPGA temperatures reached
values around 115 deg.<br>
>>> Since it looked like a readout error, I checked
the strip chart,<br>
>>> where<br>
>>> there is actually a spike in the readout at
that time, but to<br>
> values<br>
>>> of<br>
>>> the order of -10^5. See the attached plot.<br>
>>> So, it is clear that it was a readout error,
but it is strange that<br>
>>> the<br>
>>> alarm message and epics report different
values.<br>
>>> Also, according to the logbook, the electronics
was not shut down<br>
> by<br>
>>> the<br>
>>> interlocks, as should have happened if the
temperature really went<br>
>>> above<br>
>>> 100 deg.<br>
>>> So, perhaps the values reported in the alarm
messages are not the<br>
>>> correct ones?<br>
>>> Marco<br>
>>> <br>
>>> _______________________________________________<br>
>>> Dsg-rich mailing list<br>
>>> <a class="moz-txt-link-abbreviated" href="mailto:Dsg-rich@jlab.org">Dsg-rich@jlab.org</a><br>
>>>
<a class="moz-txt-link-freetext" href="https://mailman.jlab.org/mailman/listinfo/dsg-rich">https://mailman.jlab.org/mailman/listinfo/dsg-rich</a><br>
>> <br>
>> _______________________________________________<br>
>> Dsg-rich mailing list<br>
>> <a class="moz-txt-link-abbreviated" href="mailto:Dsg-rich@jlab.org">Dsg-rich@jlab.org</a><br>
>> <a class="moz-txt-link-freetext" href="https://mailman.jlab.org/mailman/listinfo/dsg-rich">https://mailman.jlab.org/mailman/listinfo/dsg-rich</a><br>
> _______________________________________________<br>
> Rich mailing list<br>
> <a class="moz-txt-link-abbreviated" href="mailto:Rich@jlab.org">Rich@jlab.org</a><br>
> <a class="moz-txt-link-freetext" href="https://mailman.jlab.org/mailman/listinfo/rich">https://mailman.jlab.org/mailman/listinfo/rich</a><br>
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<pre wrap="">_______________________________________________
Rich mailing list
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