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<div class="moz-cite-prefix">Hi All,</div>
<div class="moz-cite-prefix">inside the rich e-panel there are two
air manifolds but I do not remember if we have the possibility to
adjust the flow separately.</div>
<div class="moz-cite-prefix">What might be interesting to test is to
change the flow in the two manifolds separately in order to find
the best setup that minimizes the flow towards the detector
keeping a good safety margin on the max temperatures on the
electronic boards.</div>
<div class="moz-cite-prefix">May be I am dreaming...</div>
<div class="moz-cite-prefix">George is this possible in your
opinion?</div>
<div class="moz-cite-prefix">Hope to see you soon <br>
</div>
<div class="moz-cite-prefix">Many thanks<br>
</div>
<div class="moz-cite-prefix">Sandro<br>
</div>
<div class="moz-cite-prefix"><br>
</div>
<div class="moz-cite-prefix">Il 24/09/2019 14:23, Tyler Lemon ha
scritto:<br>
</div>
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Hello,</div>
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<br>
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<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
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From Ben and Mateo's reply, it seems the goal of the test should
be to keep the same temperatures in RICH as previous running
periods.</div>
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<br>
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<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
Ideally, the test would involve finding what airflow settings
are required to maintain ~65 C in RICH FPGAs. It may be that 900
slm is actually required to keep temperatures in the appropriate
range.<br>
</div>
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<br>
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<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
At a bare minimum, the tests should involve adjusting compressor
settings with the goal of maintaining 900 slm total flow. For
this, RICH electronics can be left off since the airflow
measurements would be the indicator of test results.
<br>
</div>
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<br>
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<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
It is as Marco said, we never tried to optimize the cooling
system. These tests would be the only way to see what is
actually needed to cool RICH and to see whether the current
cooling system could even provide enough flow for two RICH
sectors.</div>
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<br>
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<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
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- Tyler<br>
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<br>
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<br>
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<br>
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<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt"
face="Calibri, sans-serif" color="#000000"><b>From:</b> Marco
Mirazita <a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
<b>Sent:</b> Tuesday, September 24, 2019 4:18 AM<br>
<b>To:</b> Amrit Yegneswaran <a class="moz-txt-link-rfc2396E" href="mailto:yeg@jlab.org"><yeg@jlab.org></a><br>
<b>Cc:</b> Benjamin Raydo <a class="moz-txt-link-rfc2396E" href="mailto:braydo@jlab.org"><braydo@jlab.org></a>; Tyler Lemon
<a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a>; dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
<b>Subject:</b> Re: [Dsg-rich] [EXTERNAL] RICH electronics</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span
style="font-size:11pt;">
<div class="PlainText">Hi all,<br>
let me make a couple of remarks.<br>
<br>
1) The temperature limits were set to ensure a safe
operation of the <br>
whole system, which, as Ben said, includes not just the
FPGA, but <br>
cables, MAROC, external temperature close to TOF, etc. I
don't want to <br>
change these limits unless strictly necessary and only if
with no risk <br>
for the detectors.<br>
However, we know that the current running conditions are
mostly driven <br>
by one FPGA which is producing more heat (its temperature
is about 2 or <br>
3 degrees higher than the neighbors) and by chance it is
also in the <br>
hottest spot of the panel.<br>
<br>
2) The cooling system was originally designed to be able
to feed two <br>
RICH modules with one compressor, in case of failure of
the other one. <br>
We are now far from this situation. We run one RICH with
900 slm with a <br>
maximum of 1200 slm per compressor. But we never attempted
a real <br>
optimization of the air flow. For example, the lower line
is flowing <br>
less air than the upper one, while I would expect the
opposite.<br>
<br>
For these reasons, I think there could be room to optimize
the running <br>
conditions and get closer to the original design.<br>
But let me stress again that this optimization must ensure
to stay <br>
within the safety limits.<br>
<br>
Best regards,<br>
Marco<br>
<br>
<br>
<br>
<br>
Il 2019-09-24 04:12 Amrit Yegneswaran ha scritto:<br>
> given ben's last sentence<br>
> <br>
> (highlighted; i guess "it" in the sentence refers to
"the<br>
> temperature" as does "that".<br>
> from which we have it = that => i = hat or i
=tha, aah the pronouns<br>
> they are precious!)<br>
> <br>
> anyway i'm now very confused about the planned test
and the intent<br>
> thereof?<br>
> <br>
> are we thinking reducing the airflow from ~950 slm
will reduce the<br>
> temperature below 65c?<br>
> pardon my obtuseness.<br>
> <br>
> so what mods are you conjuring up tyler?<br>
> <br>
> -------------------------<br>
> <br>
> FROM: Benjamin Raydo <a class="moz-txt-link-rfc2396E" href="mailto:braydo@jlab.org"><braydo@jlab.org></a><br>
> SENT: Monday, September 23, 2019 5:33 PM<br>
> TO: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a>; Amrit
Yegneswaran <a class="moz-txt-link-rfc2396E" href="mailto:yeg@jlab.org"><yeg@jlab.org></a>;<br>
> Marco Mirazita <a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics<br>
> <br>
> Hi Tyler,<br>
> <br>
> Matteo is correct about the temperature limit of 85C
to respect the<br>
> FPGA timing constraints, but we also have fiber
cables running close<br>
> to those parts that are rated for 80C (I'd expect
some deformation<br>
> possible if we go above this for a long period).<br>
> <br>
> Can we set a safe limit of 75C for any reported FPGA
temperature for<br>
> your tests (short term limit: <1hr)? If your tests
need to run in such<br>
> a way that you want a higher limit, let us discuss
again if you don't<br>
> mind. For long term it would be great to keep it as
low as possible<br>
> and for the moment I believe we've been running with
the hottest FPGA<br>
> temp to be around 65C so don't want to see that
increase significantly<br>
> if there are any changes to the cooling.<br>
> <br>
> Hope that helps.<br>
> <br>
> Thanks,<br>
> Ben<br>
> <br>
> -------------------------<br>
> <br>
> FROM: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
> SENT: Monday, September 23, 2019 4:59 PM<br>
> TO: Amrit Yegneswaran <a class="moz-txt-link-rfc2396E" href="mailto:yeg@jlab.org"><yeg@jlab.org></a>; Marco
Mirazita<br>
> <a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a>; Benjamin Raydo
<a class="moz-txt-link-rfc2396E" href="mailto:braydo@jlab.org"><braydo@jlab.org></a><br>
> CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics<br>
> <br>
> Hi Ben,<br>
> <br>
> In October, we're planning on doing some testing to
optimize RICH's<br>
> cooling system and see what would needed to modify
the system to cool<br>
> two RICH sectors.<br>
> <br>
> With respect to the RICH readout electronics, FPGAs,
and their<br>
> timing, are there any temperature limits we should
take into<br>
> consideration when testing the cooling system?<br>
> <br>
> Thanks,<br>
> Tyler<br>
> <br>
> -------------------------<br>
> <br>
> FROM: Amrit Yegneswaran <a class="moz-txt-link-rfc2396E" href="mailto:yeg@jlab.org"><yeg@jlab.org></a><br>
> SENT: Monday, September 23, 2019 4:48 PM<br>
> TO: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a>; Marco
Mirazita<br>
> <a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics<br>
> <br>
> tyler<br>
> address fpga temp issue with ben.<br>
> i believe 60c is right at the edge of timing issues,
not sure.<br>
> -------------------------<br>
> <br>
> FROM: Dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich-bounces@jlab.org"><dsg-rich-bounces@jlab.org></a> on
behalf of Tyler Lemon<br>
> <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
> SENT: Monday, September 23, 2019 3:11 PM<br>
> TO: Marco Mirazita
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics<br>
> <br>
> Hi Marco,<br>
> <br>
> Looking back at EP temperatures during steady
operations (I picked<br>
> 3/10/2019 to 3/31/2019), Hardware Interlock RTDs were
~40 deg C and<br>
> FPGA temperatures were ~60 deg C.<br>
> <br>
> Is there a temperature increase that would be
considered acceptable?<br>
> For example if the FPGA temperatures were ~70 deg C
rather than ~60<br>
> deg C?<br>
> <br>
> The first test should be determining what flow rate
is actually<br>
> needed to maintain EP temperatures in that acceptable
range with all<br>
> RICH electronics on.<br>
> <br>
> -Tyler<br>
> <br>
> -------------------------<br>
> <br>
> FROM: Marco Mirazita
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> SENT: Monday, September 23, 2019 9:01 AM<br>
> TO: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
> CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a><br>
> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics<br>
> <br>
> Hi Tyler,<br>
> sorry, I had in mind that the replacement of the PT
was scheduled for<br>
> <br>
> last Wednesday.<br>
> <br>
> The tests we have in mind to optimize the cooling
system is basically<br>
> <br>
> what you said. But we still have to make a plan of
the specific<br>
> measurements we need. We will do this plan in the
next weeks.<br>
> Any suggestion from you and the DSG is welcome.<br>
> <br>
> Best regards,<br>
> Marco<br>
> <br>
> Il 2019-09-20 20:46 Tyler Lemon ha scritto:<br>
> > Hi Marco,<br>
> ><br>
> > The PT replacement has not been completed. It
is scheduled for next<br>
> > Wednesday September 25.<br>
> ><br>
> > As for the visit to optimize RICH running
conditions, I will not be<br>
> > at work for at least part of the week of
October 21 to October 25,<br>
> > however there should be other people from DSG
that would be able to<br>
> > help.<br>
> ><br>
> > What tests are being planned for the visit?
Would it essentially be<br>
> > varying the settings of the cooling system
(flow rate, buffer tank<br>
> > pressure, compressor output pressure) and
seeing how the<br>
> temperature<br>
> > within RICH is affected?<br>
> ><br>
> > Best regards,<br>
> > Tyler<br>
> ><br>
> > -------------------------<br>
> ><br>
> > FROM: Marco Mirazita
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> > SENT: Friday, September 20, 2019 12:21 PM<br>
> > TO: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
> > CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a>; Valery
Kubarovsky <a class="moz-txt-link-rfc2396E" href="mailto:vpk@jlab.org"><vpk@jlab.org></a>;<br>
> > marco contalbrigo <a class="moz-txt-link-rfc2396E" href="mailto:mcontalb@fe.infn.it"><mcontalb@fe.infn.it></a><br>
> > SUBJECT: Re: [EXTERNAL] RICH electronics<br>
> ><br>
> > Hi Tyler,<br>
> > do you know if Bob has completed the
replacement of the FT?<br>
> > If so, the compressor could be restarted on
Monday morning, once we<br>
> > are<br>
> > sure everything is working properly I can turn
on the RICH<br>
> > electronics<br>
> > and keep it on for the night and then make the
tests on Tuesday<br>
> > morning.<br>
> ><br>
> > As you know, we didn't have much time to
optimize the working point<br>
> > of<br>
> > the cooling system after the RICH installation,
we simply choose<br>
> > running<br>
> > conditions that ensure a safe operation of the
detector.<br>
> > But these running conditions might be
problematic with two RICH<br>
> > modules<br>
> > and definitely not sustainable in case of
failure of one of the two<br>
> > compressors.<br>
> > Therefore, also in preparation of the upcoming
CLAS12 data taking,<br>
> > I'm<br>
> > planning a visit to JLab for Dario and Sandro
to try to optimize<br>
> the<br>
> > running conditions, and to be effective this
work must be<br>
> coordinated<br>
> ><br>
> > with you and the DSG.<br>
> > The proposed dates are from October 21 to
October 31. Is this plan<br>
> ok<br>
> ><br>
> > for you?<br>
> > Thank you,<br>
> > Marco<br>
> ><br>
> > Il 2019-09-18 14:12 Tyler Lemon ha scritto:<br>
> > > Hi Marco,<br>
> > ><br>
> > > Bob Miller has scheduled the replacement
of the faulty pressure<br>
> > > transducer (PT) on the air-cooling buffer
tank for next<br>
> Wednesday,<br>
> > > September 25.<br>
> > ><br>
> > > Could the tests be scheduled to start
Thursday September 26?<br>
> > ><br>
> > > Best regards,<br>
> > > Tyler<br>
> > ><br>
> > > -------------------------<br>
> > ><br>
> > > FROM: Marco Mirazita
<a class="moz-txt-link-rfc2396E" href="mailto:Marco.Mirazita@lnf.infn.it"><Marco.Mirazita@lnf.infn.it></a><br>
> > > SENT: Wednesday, September 18, 2019 4:08
AM<br>
> > > TO: Tyler Lemon <a class="moz-txt-link-rfc2396E" href="mailto:tlemon@jlab.org"><tlemon@jlab.org></a><br>
> > > CC: dsg-rich <a class="moz-txt-link-rfc2396E" href="mailto:dsg-rich@jlab.org"><dsg-rich@jlab.org></a>;
Valery Kubarovsky<br>
> <a class="moz-txt-link-rfc2396E" href="mailto:vpk@jlab.org"><vpk@jlab.org></a>;<br>
> > > marco contalbrigo
<a class="moz-txt-link-rfc2396E" href="mailto:mcontalb@fe.infn.it"><mcontalb@fe.infn.it></a><br>
> > > SUBJECT: [EXTERNAL] RICH electronics<br>
> > ><br>
> > > Hi Tyler,<br>
> > > the RICH electronics is off since quite a
lot of time and in<br>
> > > preparation<br>
> > > of the upcoming CLAS12 running I would
like to turn it on to<br>
> verify<br>
> > > that<br>
> > > everything is still working and eventually
to take new scaler<br>
> > > calibration data.<br>
> > > I could plan this work for the beginning
of the next week.<br>
> > > In preparation for that, we should
coordinate to have all the<br>
> > systems<br>
> > ><br>
> > > ready. Would you be available to start the
compressor for the<br>
> test?<br>
> > > Thank you,<br>
> > > Marco<br>
> ><br>
> > _______________________________________________<br>
> > Dsg-rich mailing list<br>
> > <a class="moz-txt-link-abbreviated" href="mailto:Dsg-rich@jlab.org">Dsg-rich@jlab.org</a><br>
> > <a
href="https://mailman.jlab.org/mailman/listinfo/dsg-rich"
moz-do-not-send="true">https://mailman.jlab.org/mailman/listinfo/dsg-rich</a>
[1]<br>
> <br>
> <br>
> Links:<br>
> ------<br>
> [1] <a
href="https://mailman.jlab.org/mailman/listinfo/dsg-rich"
moz-do-not-send="true">https://mailman.jlab.org/mailman/listinfo/dsg-rich</a><br>
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<pre class="moz-quote-pre" wrap="">_______________________________________________
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</pre>
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<p><br>
</p>
<pre class="moz-signature" cols="72">--
-----------------------------------------
Dr. Eng. Sandro Tomassini
Istituto Nazionale di Fisica Nucleare
Laboratori Nazionali di Frascati
---Research Division---
P.O.Box 13 00044 Frascati (RM) Italy
Tel. office: +39 06 9403 2919/8089
Fax: +39 06 94032256
e-mail: <a class="moz-txt-link-abbreviated" href="mailto:sandro.tomassini@lnf.infn.it">sandro.tomassini@lnf.infn.it</a>
<a class="moz-txt-link-freetext" href="https://urldefense.proofpoint.com/v2/url?u=http-3A__www.lnf.infn.it_&d=DwMD-g&c=CJqEzB1piLOyyvZjb8YUQw&r=sLmN_kLNB8f_QBCYTgZaO1cK1zcpXSUHz0BQf_04bYk&m=Ks_koQB8zfdhAZpqWi1ulFQVWFGW3EuWLeBlPjTyTDs&s=sUK8i5XKeQizqnO1zVv4v1N6p7Mr7ouujo4N8w-3gRQ&e=">http://www.lnf.infn.it/</a>
-----------------------------------------
-- </pre>
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