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<p>Thank you Peter,</p>
<p>I will follow your advice.<br>
</p>
<br>
<div class="moz-cite-prefix">On 10/17/17 7:44 AM, Peter Bonneau
wrote:<br>
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<p>The Hardware Interlock trip latch is only reporting the low
coolant flow event at 20:27 and therefore should not have
disabled the Mpod crate controller before this event. <br>
</p>
<p>To check the Mpod crate controller and the interlock disable
signal: <br>
</p>
<p>1) To check the hardware interlock Mpod logic, you can try
disabling the inlet and outlet coolant flow interlock enables.
After disabling and at the next trip event, take screen captures
of the "Interlock Status and signal monitoring" and the "Raw
data monitoring" tabs of the Hardware Interlock Monitoring
System user interface.</p>
<p>2) To check the Mpod crate controller input inhibit signal, you
can try turning on the Mpod interlock system override key switch
on the cRio crate. This effectively shorts all the Mpod crate
enables to the +5V supply. <br>
</p>
<p>The crate enable signals share the +5V supply with the humidity
sensors. To check the stability of this supply at the time of
the last trip, I looked at the humidity signals shown in the
attached EPICS Mya archive chart. If the +5V was unstable at the
time of the trip event, there would be a large fluctuation in
the humidity measurements. No fluctuations were seen at the time
of the trip.</p>
<p><br>
</p>
<br>
<div class="moz-cite-prefix">On 10/16/2017 2:05 PM, Yuri Gotra
wrote:<br>
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<p>Thank you Peter,</p>
<p>I still see the same picture as it was last week, see the
attached picture: HV R1:outinhibit was first (20:04), then
fast powering off HV and LV, then (because the heat source,
LV, was removed) temperature gradually decreased till (as
designed) the ambient temperature soft interlock stopped the
chiller (20:27). <br>
</p>
<p>The question is why R1 HV outinhibit was issued. Please let
me know your suggestions on further debugging. Thank you<br>
</p>
<br>
<div class="moz-cite-prefix">On 10/16/17 11:21 AM, Peter Bonneau
wrote:<br>
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<div>We had another trip of the SVT on 10/15/2017 at 20:27.<br>
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<div><br data-mce-bogus="1">
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<div>Analysis of the trip for the Hardware Interlock System
showed that low coolant flow was detected followed by the
shutdown of all low and high voltage. This is the correct
response for the interlock system. The interlock system
can not stop coolant flow. <br>
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<div><br data-mce-bogus="1">
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<div>As shown in the attached EPICS Mya archive chart, a
slow rise in coolant temperature occurred after the trip.
<br>
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<div><br data-mce-bogus="1">
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<div><br data-mce-bogus="1">
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<div>Peter<br>
</div>
<div><br data-mce-bogus="1">
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<div><br>
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<hr id="zwchr" data-marker="__DIVIDER__">
<div data-marker="__HEADERS__"><b>From: </b>"Peter Bonneau"
<a class="moz-txt-link-rfc2396E"
href="mailto:bonneau@jlab.org" moz-do-not-send="true"><bonneau@jlab.org></a><br>
<b>To: </b>"Yuri Gotra" <a class="moz-txt-link-rfc2396E"
href="mailto:gotra@jlab.org" moz-do-not-send="true"><gotra@jlab.org></a>,
<a class="moz-txt-link-abbreviated"
href="mailto:dsg-svt@jlab.org" moz-do-not-send="true">dsg-svt@jlab.org</a><br>
<b>Sent: </b>Friday, October 13, 2017 7:38:36 AM<br>
<b>Subject: </b>Re: SVT outinhibit<br>
</div>
<div><br>
</div>
<div data-marker="__QUOTED_TEXT__">Yuri:<br>
<br>
I checked on the hardware interlock system system this
morning and it's <br>
running normally (no trips overnight).<br>
<br>
After a system trip and before resetting, we need screen
captures of the <br>
"Interlock Status and signal monitoring" and the "Raw data
monitoring" <br>
tabs of the Hardware Interlock Monitoring System user
interface for <br>
troubleshooting. We need to know which signal is causing
the tripping.<br>
<br>
The last time we had an issue like this (1/31/2017) , the
problem was <br>
caused by a loose connection to the external coolant
system monitoring <br>
electronics (Proteus Industries sensor and Florite 990x
Controller.)<br>
<br>
As mentioned back in January, we don't have spares for the
external <br>
coolant monitoring electronics. I recommend we purchase
spares for this <br>
system.<br>
<br>
Peter<br>
<br>
On 10/12/2017 8:31 PM, Yuri Gotra wrote:<br>
> Dear Peter,<br>
><br>
> We had another crate inhibit issue this evening.
Software interlocks <br>
> were ok, chiller running.<br>
><br>
> HV inhibit was red and all HV channel inhibits had
errors. HV and LV <br>
> ramped down.<br>
><br>
> On the screenshot you could see
B_SVT_HV_R1:outinhibit major <br>
> HIHI_alarm at 20:06.<br>
><br>
> Please let us know your suggestions on debugging this
issue. Thank you<br>
><br>
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