<html><body><div style="font-family: arial,helvetica,sans-serif; font-size: 12pt; color: #000000"><div>Only the crate inhibits come from the hardware interlock system which are working according to the test just done.<br></div><div><br data-mce-bogus="1"></div><div>Nathan, where is the HV channel output inhibits coming from? Read-back from the HV modules?<br data-mce-bogus="1"></div><div><br></div><hr id="zwchr" data-marker="__DIVIDER__"><div data-marker="__HEADERS__"><b>From: </b>"Yuri Gotra" <gotra@jlab.org><br><b>To: </b>"dsg-svt" <dsg-svt@jlab.org><br><b>Cc: </b>"Nathan Baltzell" <baltzell@jlab.org><br><b>Sent: </b>Tuesday, July 24, 2018 11:28:50 AM<br><b>Subject: </b>Re: [dsg-svt] [Dsg-hallbgas] Gas System cRIOs<br></div><div><br></div><div data-marker="__QUOTED_TEXT__"><p>MPOD crates rebooted.<br></p><p>Interlock connector checked. When disconnected crate inhibit appears in the SVT HW interlocks GUI. <br></p><p>Still cannot clear HV channel output inhibits.</p><p>Not clear yet if it is EPICS or hardware failure. <br></p><br><div class="moz-cite-prefix">On 7/24/18 11:11 AM, Peter Bonneau wrote:<br></div><blockquote cite="mid:1717742662.2442631.1532445060705.JavaMail.zimbra@jlab.org"><div style="font-family: arial,helvetica,sans-serif; font-size:
12pt; color: #000000" data-mce-style="font-family: arial,helvetica,sans-serif; font-size: 12pt; color: #000000;"><div>The manual override switches are turned on as part of the hardware Interlock upgrade.<br></div><div>The switches bypass the hardware interlock system and directly shorts the Mpod crate enable signals to +5V.<br></div><div>We're reading back that bypass voltage on an ADC in the cRio crate and it's measuring +5V so they should be enabled.<br></div><div><br></div><div>Please check the interlock connector on the front of the crates.</div><div>Also check the Mpod crates, controllers, and EPICS interface.<br></div><div><br></div><div>The cRio upgrade is in progress so rebooting and loss of contact via EPICS will be occurring.<br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><br></div></blockquote><br> <br>_______________________________________________<br>dsg-svt mailing list<br>dsg-svt@jlab.org<br>https://mailman.jlab.org/mailman/listinfo/dsg-svt<br></div></div></body></html>