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<p style="margin-top:0;margin-bottom:0">Hi Mike,</p>
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<p style="margin-top:0;margin-bottom:0">I am unsure of how to export routines to .L5X from version 16 of RSLogix 5000 (since this is for HMS), or if that can even be done. I know it can be done in version 20. Attached is the .csv file of the tag names and
the ACD file which you could use to copy/paste the routines into the program.</p>
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<p style="margin-top:0;margin-bottom:0">Regards,</p>
<p style="margin-top:0;margin-bottom:0">Amanda<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Steven Lassiter<br>
<b>Sent:</b> Friday, January 4, 2019 10:39 AM<br>
<b>To:</b> Amanda Hoebel<br>
<b>Subject:</b> Re: Revised routine</font>
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<p style="margin-top:0px; margin-bottom:0px">Hello Amanda,</p>
<p style="margin-top:0px; margin-bottom:0px"><br>
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<p style="margin-top:0px; margin-bottom:0px"> can you send me the routines (*.L5x) and tags (*.csv) (controller vs program, names and type) in a separate file.</p>
<p style="margin-top:0px; margin-bottom:0px">I will load into the test PLC and test it out</p>
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<p style="margin-top:0px; margin-bottom:0px">thanks</p>
<p style="margin-top:0px; margin-bottom:0px">Steven<br>
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<div id="x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Dsg-hallc_controls <dsg-hallc_controls-bounces@jlab.org> on behalf of Amanda Hoebel <amandah@jlab.org><br>
<b>Sent:</b> Wednesday, November 28, 2018 3:27:16 PM<br>
<b>To:</b> dsg-hallc_controls@jlab.org<br>
<b>Subject:</b> [Dsg-hallc_controls] Revised routine</font>
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<div>Hi Mike,<br>
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<div><br>
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<div>Attached are the PDFs of the revised function block diagrams and ladder logic.<br>
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<div><br>
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<div>Regards,<br>
</div>
<div>Amanda<br>
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<div><br>
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<div><b>From: </b>"Mike Fowler" <fowler@jlab.org><br>
<b>To: </b>"dsg-hallc controls" <dsg-hallc_controls@jlab.org><br>
<b>Sent: </b>Monday, November 12, 2018 8:43:23 AM<br>
<b>Subject: </b>Re: [Dsg-hallc_controls] DSG's PLC tasks report<br>
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<div class="x_x_moz-cite-prefix">>>>DSG's weekly report<br>
>>>Modified to PLC routine to ramp down the quadrupoles when interlock is enabled<br>
(PSU_Sum_Interlock bit =1).<br>
Not required. The existing PLC code ramps down the power supply when there is an interlock.<br>
<br>
>>>>Added pulse-timer that waits for 100 ms and then transmits trigger pulse to enable the sending of<br>
0 A current value.<br>
Not required.<br>
<br>
The new current regulation code should go into standby waiting for new input.<br>
The code should not try to control the power supply when/if there is an interlock.<br>
<br>
Cheers,<br>
Mike<br>
<br>
<br>
<br>
<br>
On 11/9/2018 4:56 PM, Pablo Campero wrote:<br>
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Hello,</div>
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I have attached the DSG's weekly report for Hall C-PLC tasks.</div>
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<br>
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Best Regards,</div>
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Pablo</div>
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