[dsg-hdice] DSG HDice Schedule

[Peter Bonneau]

Hello, 

The DSG HDice work schedule is attached to this email. 




During the development of synchronization for the external current shunt, a hardware limitation in the lock-in amplifier has been found. 


When triggered externally at frequencies ~ >300Hz, the lock-in amplifier's trigger efficiency is less than 100%. 


Two lock-in amplifiers were tested and gave the same result. 


The trigger efficiency needs to be 100% so the data from the current shunt and the lock-in amplifier are synchronized in time up to max 16.3K buffer depth. 

If a shorter scan time is necessary, the number of data points (DP/sec) will be reduced to achieve 100% trigger efficiency. 

However, when triggering externally, we are not limited to the frequency step size only available with the internal lock-in amplifier's oscillator. 

The external trigger frequency can be set via the CT-Box up to the 100% trigger efficiency limit, which is reached at a frequency of ~ 300Hz. 















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