[Halla_daq] VETROC firmware V7.2 (vfTDC)

[J. William Gu]

Hi,

The vfTDC firmware V7.2 is ready.  It was copied to /group/da/distribution/coda/Firmware/vf3tdc72.svf.

The firmware history file vfTDCFirmwareHistory can also be found there.  The manual (vftdc.doc, vftdc.pdf) can be found at /group/da/distribution/pdfs/vftdc

The main changes are the trigger logic addition.  The very top connector on the front panel (right half) is used for the trigger logic outputs
  pin#1/2: OR of connector#A (top front panel) 32-channels, 4ns wide output, channel rising edge sensitive, channel enabled by vme register 0x60;
  pin#3/4: OR of connecotr#B (top mezz board) 32-channels, 4ns wide, channel rising edge sensitive, channels enabled by vme register 0x64;
  pin#5/6: OR of connector#C (bottom front panel) 32-channels, 4ns wide output, channel rising edge sensitive, channel enabled by vme register 0x68;
  pin#7/8: OR of connecotr#D (bottom mezz board) 32-channels, 4ns wide, channel rising edge sensitive, channels enabled by vme register 0x6C;
  pin#9/10: OR of connector#VA (VME P2IO board A) 32-channels, 4ns wide output, channel rising edge sensitive, channel enabled by vme register 0x70;
  pin#11/12: OR of connecotr#VC (VME P2IO board C) 32-channels, 4ns wide, channel rising edge sensitive, channels enabled by vme register 0x74;
  pin#13/14: OR of all the six connector_level outputs (pin#1-12), width adjusted (by vme register 0x78 bit15-8);
  pin#15/16: OR of output pin#13/14 and Generic_input (pin#25/26).

The hit pattern is NOT implemented, as 192 bits is equivalent to 6 32-bit words, and mostly zeros.  The readout should be less if the actual TDC of the active channel is readout.

The option to mask off (disable) the rising edge TDC or falling edge TDC was implemented.  Now, We have the option to read out one edge only to decrease data size.

There might be timing changes in the readout, as the Readout_trigger/Calibration/Sync_reset from front panel inputs are polarity inverted on the PCB.  The polarity of these three signals are reverted back in the FPGA at the new firmware (V7.2).

One surprise, the readout window is 16-bit, so it can be as long as 260 us.  But as the firmware does not deal with overlapping events, the trigger rule#1 should be set accordingly.

Thanks.

William


----- Original Message -----
> From: "Alexandre Camsonne" <camsonne at jlab.org>
> To: "halla daq" <halla_daq at jlab.org>
> Sent: Thursday, October 12, 2017 11:26:44 AM
> Subject: [Halla_daq] DAQ meeting Friday October 13th 1PM F326-327

> Hello,
> 
> we will have DAQ meeting this week.
> 
> Rough agenda :
> 
> 1:00 PM VETROC Compton update ( Marco )
> 1:15 PM FADC deadtime measurement update ( Ed)
> 1:30 PM FADC test in HRS (Hanjie)
> 1:45PM HRS busy study (Michael)
> 2:00PM Tritium trigger (Florian)
> 2:15PM DAQ task list (Evan )
> 
> 
> Best regards,
> 
> Alexandre
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