<html><body><div style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #000000"><div>Hello Ruben,</div><div><br data-mce-bogus="1"></div><div>Yes I can continue with the test. As today I talked with Nick we can force some of the thresholds in the PLC program in order to clean all the interlocks and be able to continue with the test.</div><div><br data-mce-bogus="1"></div><div>Best Regards </div><div>Pablo Campero </div><div><br></div><hr id="zwchr" data-marker="__DIVIDER__"><div data-marker="__HEADERS__"><b>From: </b>"Ruben Fair" <rfair@jlab.org><br><b>To: </b>"Nicholas Sandoval" <sandoval@jlab.org><br><b>Cc: </b>"Pablo Campero Rojas" <campero@jlab.org>, "hallb-solenoid" <hallb-solenoid@jlab.org><br><b>Sent: </b>Tuesday, October 4, 2016 10:50:01 AM<br><b>Subject: </b>Re: [Hallb-solenoid] cRIO communication Lost<br></div><br><div data-marker="__QUOTED_TEXT__"><div style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #000000"><div>So Pablo and Tyler - can you please continue with the other interlock checks?<br></div><br><div>Ruben<br></div><br><br><hr id="zwchr"><div><b>From: </b>"Nicholas Sandoval" <sandoval@jlab.org><br><b>To: </b>"Pablo Campero Rojas" <campero@jlab.org><br><b>Cc: </b>hallb-solenoid@jlab.org<br><b>Sent: </b>Tuesday, October 4, 2016 10:37:46 AM<br><b>Subject: </b>Re: [Hallb-solenoid] cRIO communication Lost<br></div><br><div>Hello Pablo,<br><br>Yes you can continue the testing. You do not need the cRIO for VT/System cable interlock checks. The software QD has been increased as well.<br><br>Best Regards,<br><br>Nick<br><br>----- Original Message -----<br>From: "Pablo Campero Rojas" <campero@jlab.org><br>To: "Nicholas Sandoval" <sandoval@jlab.org><br>Cc: hallb-solenoid@jlab.org<br>Sent: Tuesday, October 4, 2016 10:30:30 AM<br>Subject: cRIO communication Lost<br><br>Hi Nick, <br><br>I made the resets necessary to restart the communication between the PLC and cRIO, But it seems that there are problems with the LV cRIO, I don't see any update count coming in the PLC program. <br>And I can't continue making the interlock check list until issues with regard to the Voltage Taps and the LV cRIO are solved. <br><br>I'm going to leave the lap top in the TEDF building. <br><br><br>With Regards <br>Pablo Campero<br>_______________________________________________<br>Hallb-solenoid mailing list<br>Hallb-solenoid@jlab.org<br>https://mailman.jlab.org/mailman/listinfo/hallb-solenoid</div></div><br></div></div></body></html>