<html><body><div style="font-family: arial,helvetica,sans-serif; font-size: 12pt; color: #000000"><div>Good Afternoon,<br></div><div><br data-mce-bogus="1"></div><div>I ran the magnet up to 10A. It seems the PLC current leads the PXI current on the archiver (see attached)<br data-mce-bogus="1"></div><div><br></div><div data-marker="__SIG_PRE__">Tim Whitlatch<br>Hall D Engineer<br>Jefferson Lab<br>600 KELVIN DR STE 5<br>Newport News, VA 23606-4468 <br>757-269-5087</div><br><hr id="zwchr" data-marker="__DIVIDER__"><div data-marker="__HEADERS__"><b>From: </b>"Brian Eng" <beng@jlab.org><br><b>To: </b>"Hovanes Egiyan" <hovanes.egiyan@gmail.com><br><b>Cc: </b>halld-controls@jlab.org<br><b>Sent: </b>Thursday, September 6, 2018 12:18:51 PM<br><b>Subject: </b>Re: [Halld-controls] PXI Time Stamps<br></div><br><div data-marker="__QUOTED_TEXT__">I tried disabling/enabling the setting I thought might correct the offset on the PXI; which naturally had no effect (at least on the PXI controller time properties, still showing 34 sec faster).<br><br>I've filed a support ticket with NI to see if there's some other way to do something about this offset.<br><br>Currently it is in the opposite setting it was previously, so maybe it's good on the EPICS side now?<br>If someone wanted to put a small amount of current in the magnet to compare the PVs with the PXI data we'd know for sure.<br><br>----- Original Message -----<br>> From: "Hovanes Egiyan" <hovanes.egiyan@gmail.com><br>> To: "Brian Eng" <beng@jlab.org><br>> Cc: halld-controls@jlab.org<br>> Sent: Tuesday, September 4, 2018 10:42:27 AM<br>> Subject: Re: [Halld-controls] PXI Time Stamps<br><br>> The timestamps in the ROOT files should be from PXI, the IOC is supposed<br>> to keep that timestamp.<br>> <br>> I do not know exactly how PXI decides what time to put on the 10K long<br>> array.<br>> <br>> Hovanes.<br>> <br>> <br>> <br>> On 09/04/2018 10:22 AM, Brian Eng wrote:<br>>> No, since we don't really care about the UTC <-> TIA offset it would just be<br>>> updating the PXI to (hopefully) undo that offset that the PLC uses. So far<br>>> Rockwell has said it is hard-coded and we can't modify it.<br>>><br>>> However, the PVs seem backwards to me (PXI is ~30 sec slower than the PLC, when<br>>> it should be faster). See attached screenshots.<br>>><br>>> Are there any timestamps from the SOE on the last dump? On the FastDAQ ROOT<br>>> program, where are the timestamps coming from? The IOC or the PXI? If it comes<br>>> from the IOC then we don't need to do anything with the PXI.<br>>><br>>> I have no plans on doing anything with the PLC unless/until they have a firmware<br>>> we can set that offset to 0.<br>>><br>>> ----- Original Message -----<br>>>> From: "Hovanes Egiyan" <hovanes.egiyan@gmail.com><br>>>> To: halld-controls@jlab.org<br>>>> Sent: Tuesday, September 4, 2018 9:47:23 AM<br>>>> Subject: Re: [Halld-controls] PXI Time Stamps<br>>>> Brian, are you going to change the firmware on a PLC module? I did not quite<br>>>><br>>>><br>>>> understand what is going to be upgraded and rebooted.<br>>>><br>>>><br>>>> Hovanes.<br>>>><br>>>> On 09/04/2018 09:42 AM, Beni Zihlmann wrote:<br>>>><br>>>><br>>>> I think yes we should do this.<br>>>><br>>>> On 09/04/2018 09:36 AM, Timothy Whitlatch wrote:<br>>>><br>>>><br>>>><br>>>> Hi Brian,<br>>>><br>>>> We will have time this week to reboot the PXI (Just not today).<br>>>><br>>>> Hovanes and Beni, do you think we should implement the fix this week?<br>>>><br>>>><br>>>> Tim Whitlatch<br>>>> Hall D Engineer<br>>>> Jefferson Lab<br>>>> 600 KELVIN DR STE 5<br>>>> Newport News, VA 23606-4468<br>>>> 757-269-5087<br>>>><br>>>><br>>>> From: "Brian Eng" <beng@jlab.org><br>>>> To: "Hall D Controls" <halld-controls@jlab.org><br>>>> Sent: Thursday, August 30, 2018 1:46:47 PM<br>>>> Subject: [Halld-controls] PXI Time Stamps<br>>>><br>>>> We recently discovered that the time used by the PLCs has a offset to it which<br>>>> causes them to use/provide an incorrect time.<br>>>><br>>>> It manifests itself in 2 ways:<br>>>> 1) If the CC server is the master the PLC will be 34 seconds fast<br>>>> 2) if the PLC is the master any devices on the same subnet will be 34 seconds<br>>>> fast<br>>>><br>>>> That 34 seconds is hard-coded in the PLC ethernet module and only changed by<br>>>> upgrading the firmware (but it still won't be user adjustable). It comes from<br>>>> the offset between UTC & TAI time when the module was purchased.<br>>>><br>>>> Currently we're operating in the second configuration.<br>>>><br>>>> There is an option to correct this offset with Linux based NI devices, but I<br>>>> haven't yet tested it with the other OSes (namely the PXI which uses Phar Lap).<br>>>><br>>>> Unfortunately even if I can remove this offset it will require rebooting the<br>>>> PXI, so my question is should I try pursuing fixing this or is knowing that<br>>>> there is a fixed & constant offset good enough for now?<br>>>><br>>>><br>>>><br>>>><br>>>> P.S. This isn't like the earlier time problems we had where the time would<br>>>> slowly wander off, this is a fixed value with only the error of PTP coming into<br>> >> play which should be at the sub-ms level.ls<br>_______________________________________________<br>Halld-controls mailing list<br>Halld-controls@jlab.org<br>https://mailman.jlab.org/mailman/listinfo/halld-controls<br></div></div></body></html>