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from Ben Raydo:<br>
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<td>CAEN 1290 TDC</td>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">Date: </th>
<td>Tue, 14 Apr 2015 14:52:59 -0400 (EDT)</td>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">From: </th>
<td>Benjamin Raydo <a class="moz-txt-link-rfc2396E" href="mailto:braydo@jlab.org"><braydo@jlab.org></a></td>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">To: </th>
<td>Mark Ito <a class="moz-txt-link-rfc2396E" href="mailto:marki@jlab.org"><marki@jlab.org></a></td>
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<pre>Here's how I figured the 1290 TDC resolution when using the 41.666MHz clock from the TI:
>From the CAEN manual I gather:
TDC nominal bin size = 1 / (REF_CLK * 8 * 32 * 4)
Where REF_CLK = 41.666666MHz for you
8 is the reference clock PLL multiplier (to get ~320MHz)
32 is the number of delay elements in the TDC channel delay line
4 is the number of TDC channels to achieve the very high resolution ~25ps mode
So from this I get a bin size of: 23.4375ps
I don't know if it's exactly right, but it seemed like a good fit when I was measuring the accelerator RF period/phase (though I did it in 100ps resolution mode). I hope that helps.
Ben
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