[Halld-online] Front-end board data format proposal and adoption

[Fernando J Barbosa]

Hi Elliott,

The format has been set (Dave and ED) for those working on the FPGAs. 
The only part missing is the Hall D final request (if there is such a 
thing, you are right) for the algorithms. Certainly, I agree that the 
timelines need to be firmed up - there will not be any changes (schedule 
and resources) after the rebaseline is implemented.

Best regards,
Fernando

On 3/1/2013 3:34 PM, Elliott Wolin wrote:
> Hi Fernando,
>
> At recent meetings it was definitely not clear all the FPGA 
> programmers had agreed to this format (Dave A wasn't sure, even Chris 
> needed to talk to his guys).  The purpose of my note is to make sure 
> this is clear to all involved and establish a timeline.
>
> Also, Dave did not distribute the note to many in the Online group.
>
> What do you mean by "the Hall D final request?"  If you are referring 
> to the data format then Dave and Ed's proposal is what we want (to the 
> best of my knowledge).  Or are you referring to final algorithms in 
> the FPGA's?  If the latter I understand we are not ready to make a 
> final request.
>
> Thanks,
>
>
>
> On 03/01/2013 03:23 PM, Fernando J Barbosa wrote:
>> Hi Elliott,
>>
>> David already distributed this.
>>
>> For the latest on schedules, refer to my presentation to the 
>> collaboration.
>>
>> FPGA programmers already know what to do regarding the data format. 
>> The only part missing is the Hall D final request.
>>
>> Best regards,
>> Fernando
>>
>>
>> On 3/1/2013 3:07 PM, Elliott Wolin wrote:
>>> Hi,
>>>
>>> Attached is Dave A's and Ed's proposal for a consistent data format 
>>> for all JLab front-end modules.  At the last Online meeting we were 
>>> led to believe all JLab modules that get read out over the VME 
>>> backplane would implement this format (FADC25, FADC125, F1TDC, TI, 
>>> TS, etc).  We are proceeding as if this is the case.
>>>
>>> Further, we expect to begin reading out detectors this summer, 
>>> probably BCAL and FCAL first (check with Fernando for our crate 
>>> installation schedule).  We would very much like this format to be 
>>> implemented by the time the crates are installed.
>>>
>>> FPGA programmers:  please let me know ASAP if you are NOT planning 
>>> to implement this format, or if you won't be able to implement it by 
>>> the time your modules get installed in Hall D and we begin reading 
>>> them out.  We very much do not want to have to deal with multiple 
>>> formats for the same module (e.g. the June 2013 format, the Mar 2015 
>>> format, whatever).
>>>
>>> Finally, we are developing simulation, readout and analysis code 
>>> that expects this format, so we need to know ASAP if it will change.
>>>
>>> Thanks,
>>>
>>
>

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