[Halld-pid] f1TDC timing resolution

[Beni Zihlmann]

Hi All,
to follow up on the discussion about the timing resolution of our F1TDC
I looked at the data I took to test the Hamamatsu H10534 PMT.
Attached is a plot that shows the timing difference between the trigger
signal going to the TI board and the trigger signal output from the TI
board. The Gaussian fit gives a width of 36.7ps while the position is
31.85 ns. This means that the TI response time to the triggers was 31.85ns
with a timing resolution of 36.7ps. This resolution includes the timing 
jitter
of the TI board as well as the intrinsic timing resolution of the F1TDC.
In other words the intrinsic timing resolution of the F1TDC is expected
to be better than 36.7ps.

On a side note: looking at the open PMT and its base the active base 
circuitry
                          is based on 3 transistors.
cheers,
Beni
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