[Halld-tagger] F1TDC unlocking

[Richard Jones]

Sean,

Have a look at https://logbooks.jlab.org/entry/3402982. In that exercise, I
was trying to use the tdc hit spectra in the TAGM to compute a
high-resolution Fourier transform of the beam time structure, and look for
harmonics associated with other halls than hall d. In the process, I needed
to establish a "standard clock" whose phase is locked to the accelerator
clock and delivers a ps-resolution time for every hit from a single clock
running continuously over a period of days starting at some instance, say
for instance, 12:00 noon on Tuesday. By late in the week, this clock has
seen 1e17 ps go by, so I was looking for a precision of a part in 1e17,
which is a challenge to try to do. I do not pretend that the machine clock
has absolute accuracy of a part in 1e17, but using that clock to define the
scale of time, to measure events in the hall to that kind of precision. In
order to achieve this, I had to continuously update the free-running
oscillator in the F1TDC of every card I was monitoring and keep track of
its phase wrt the master clock. The details are in that logbook entry, but
basically it presents an algorithm for using the rf measurements in the PS
events (or any other continuous stream of events) to continuously track the
drifts in the internal F1TDC oscillator. As you can see, even when it is
locked, it drifts by several microseconds over a period of a run, as shown
in the plots in that logbook entry.

The job I was trying to do is more challenging in some ways, but the
problem we have when the F1TDC chip comes out of lock is solved by the same
procedure I think, provided that the fluctuations in the unlocked clock are
not too large, where "large" means greater than 32 ns of drift from one
event to the next. As long as the drift is only a few ns between events,
this procedure will take care of it. What you will get out is an average
rate of this clock since the last event, which at reasonably high trigger
rate compared to the drift time can be continuously averaged to give a high
resolution updated estimate for the instantaneous clock period of the
unlocked F1TDC oscillators.

Comments on this would be welcome.

-Richard J.

On Wed, Mar 15, 2017 at 4:04 PM, Sean Dobbs <s-dobbs at northwestern.edu>
wrote:

> Hi Richard,
>
> You mentioned at the analysis meeting today that you had a mitigation for
> the F1TDC unlocking problem, would you mind explaining more about it?  I
> haven't fully understood the ramifications of what is happening with the
> chips when this happens.
>
> Thanks,
> Sean
>
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