% The SCAM registers provide the user with control and status of each of % % the 3 laser guns, as well as the status of the two Accelerator PSS % % (personnel safety-system) inputs and FSD (fast-shutdown) inputs for the % % Accelerator and each Hall. The Accelerator register and each individual % % Hall register has two bits that define the "type" of beam each hall will % % receive. % % % % The mode of operation in the Accelerator register determines the highest % % level that any hall may be operated at. For example, if the accelerator % % is in CW mode, any hall may be set to viewer-limited, tune, or CW mode. % % Pass/User mode would not be permitted. % % % % Should the Accelerator register be placed to a lower mode of operation, % % all Hall registers will also drop to that same mode "IF" operating at a % % higher mode. If at the same or lower mode, the halls remain unchanged by % % a change in the ACC operating mode. These actions are implemented in % % firmware in the register logic defined in this subdesign. % % % % ************************************************************************* % % ************************************************************************* % % Permissible Beam "modes" and bits in order of priority are as shown: % % ACC & Hall Reg.s B-5, B-4 "Beam mode" % % 0 0 Viewer-limited % % 0 1 Tune % % 1 0 CW Beam % % 1 1 Pass/User % % % % ************************************************************************* % % VEIWER-LIMITED MODE % % Minimum Beam-Pulse of 250-ns, settable by VIEWER-LIMITED REGISTER bits % % (5-0) in 250-ns increments to a maximum of 15.750-us. The DEFAULT value % % is 250-ns. Beam is referenced to any one of the selectable frequencies % % or harmonics described below in the BEAM-SYNC and HARMONIC REGISTERS. % % % % ************************************************************************* % % TUNE MODE % % Fixed Beam-Pulse of 250-ns, followed by settable no-beam time of 98.5-us % % to 100.375-us in 125-ns steps, and followed by a "marker-pulse" of beam % % from 5.5-us to 3.625-us in length. The timing value is obtained from the % % TUNE-DELAY REGISTER. The DEFAULT value is 99.5-us. The total period of % % Beam and Modulation output signal times is fixed at 354.00-us. Beam is % % referenced to any one of the selectable frequencies or harmonics % % described below in the BEAM-SYNC and HARMONIC REGISTERS. % % % % ************************************************************************* % % CW MODE % % Beam is continuously enabled with 100 percent modulation. A Beam-sync % % output signal is generated and is referenced to any one of the selectable % % frequencies or harmonics described below in the BEAM-SYNC and HARMONIC % % REGISTERS. % % % % ************************************************************************* % % Pass/User MODE % % Beam pulses and modulation is determined by settings of the Mizar timing % % registers. Beam is referenced to any one of the selectable frequencies % % or harmonics described below in the BEAM-SYNC and HARMONIC REGISTERS. % % % % ************************************************************************* % % ************************************************************************* % % PSS & FSD FAULTS % % The Accelerator register provides status bits for accelerator FSD and PSS % % faults, while the Hall registers each provide only an FSD status bit. A % % fault on a Hall FSD input causes beam to that hall to be turned off and % % the fault to be latched in the associated Hall register. If the input % % fault is cleared, the fault status bit may then be cleared by writing a % % "GO" to the Hall register. % % % % The Accelerator register operates similarly with both its FSD and PSS % % faults, except that beams to ALL Halls are shut off and remain disabled % % until all faults in the Accelerator register are cleared. % % % % ************************************************************************* % % ************************************************************************* % % BEAM-SYNC REGISTER % % Write-only bit-1 of the Beam-Sync register (Read-only bit-6 of Harmonic % % Register) is used to select the accelerator beam-sync output signal. If % % the bit is 0 (default), either the AC line-sync or the internal 57-60 Hz % % selection will be used (selected by bit-0, described further below). If % % bit-0 is 1, the Mizar's programmable beam-sync output will be selected. % % Note that the Mizar itself uses the bit-0 selection as the "start" for % % generation of the its output sync signal. % % % % Write-only bit-0 of the Beam-Sync register (Read-only bit-7 of Harmonic % % Register) is used to select between using the AC line-sync input or the % % internally-generated 57-60 Hz signal as the input to the bit-1 selection % % of the accelerator beam-sync output signal. % % % % ************************************************************************* % % ************************************************************************* % % HARMONIC REGISTER % % Bits 1-0 of the Harmonic reg. are used to select a sub-harmonic output % % frequency of the 60Hz line input. This output signal is also the Mizar % % input sync signal. All modes of beam operation may be selected at any of % % the harmonic frequencies listed below. Valid selection are as follows: % % % % Value Selected Freq. Value Selected Freq. % % 00 (default) 60 Hz 01 30 Hz % % 10 15 Hz 11 10 Hz % % % % Bits 3-2 of the Harmonic reg. are used to select an off-line sync % % frequency derived from an on-board clock oscillator. This signal may be % % used instead of line_sync as the accelerator beam sync. Valid selectable % % frequencies are as follows: % % % % Value Selected Freq. Value Selected Freq. % % 00 (default) 60 Hz 01 59 Hz % % 10 58 Hz 11 57 Hz % % % % Bits 5 & 4 are used as bits 1 & 0 respectively by the BEAM-SYNC register. % % see the full desription below. % % % % Read-only bit-6 of the Harmonic Register (Write-only bit-1 of the % % Beam-sync Register) indicates the selection status of the beam-sync % % signal. If the bit indicates 0 (default), the AC line-sync or internal % % 57-60 Hz signal will drive (indicated by bit-7) the beam-sync output. % % A logic 1 indicates that the Mizar is providing the beam-sync signal. % % % % Read-only bit-7 of the Harmonic Register (Write-only bit-0 of the % % Beam-sync Register) indicates the selection status between the AC % % line-sync input and the internally generated 57-60 Hz signal. A logic 0 % % (default) indicates that the 60 Hz AC line-sync is selected. A logic 1 % % indicates that the 57-60 HZ signal is selected. % % % % ************************************************************************* % % ************************************************************************* % % VIEWER-LIMITED REGISTER % % Bits 5-0 of the Viewer-Limited register are used to select the duration % % of the gun-interface output beam pulse when operating in Viewer-limited % % Mode. The pulse length is selectable from 250-nsec (default) to % % 15.750-usec in 250-nsec increments. Some valid values are shown below: % % % % Value Pulse Duration Value Pulse Duration % % 1 (default) 250-ns 2 500-ns % % 8 2.000-us 20 5.000-us % % 40 10.000-us 63 (max) 15.750-us % % % % ************************************************************************* % % ************************************************************************* % % TUNE-DELAY REGISTER % % Bits 3-0 of the Tune-Delay register are used to select the beam-pulse % % time period of the "marker" at the end of the "TUNE" mode of beam % % operation The time period is selectable in 125-nsec increments. % % Valid selection are as follows: % % % % Value Marker Pulse Width Value Marker Pulse Width % % 0 5.500-us 1 5.375-us % % 2 5.250-us 3 5.125-us % % 4 5.000-us 5 4.875-us % % 6 4.750-us 7 4.625-us % % 8 (default) 4.500-us 9 4.375-us % % A 4.250-us B 4.125-us % % C 4.000-us D 3.875-us % % E 3.750-us F 3.625-us % % % % ************************************************************************* % % ************************************************************************* % % ** ACC & HALL Registers (x4) - Beam Enable Bit Assignments (write-only) % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % XX XX XX XX XX XX XX "GO" % % % % ************************************************************************* % % ** ACC Register - Bit Assignments (D7 is read-only) % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % ACC XX BEAM BEAM P-GUN ACC ACC ACC % % "GO" MODE-1 MODE-0 TEST PSSA PSSB FSD % % % % ************************************************************************* % % ** HALL Registers (x3) - Halls A, B, C Bit Assignments (D7 is read-only) % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % HALL XX XX XX XX BEAM BEAM HALL % % "GO" MODE-1 MODE-0 FSD % % % % ************************************************************************* % % ** Legacy Register **************** BEAM-SYNC REGISTER BITS % % These two bits "live" in the HARMONIC Reg (bits 5 & 4), but are written % % to by EPICS at address 7141 (bits 1 & 0). They are are read by EPICS at % % address 7143 (bits 6 & 7). The reason why this was done is long forgotten. % % Should be fixed someday when any major update is made. RJF, 01/12/06 % % ************************************************************************* % % ** BEAM-SYNC Register - BEAM-SYNC Bit Assignments (write-only) % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % XX XX XX XX XX XX 0=LINE-SYNC 0=LINE-SYNC % % 1=MIZAR-SYNC 1=OFF-SYNC % % % % ************************************************************************* % % ** HARMONIC Register - Bit Assignments (D7,D6 are read-only) % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % LINE/OFF LINE/MZR see see OFF-SYNC OFF-SYNC HARM-1 HARM-0 % % SYNC-SEL SYNC-SEL above above FREQ-1 FREQ-0 % % % % ************************************************************************* % % ** VIEWER-LIMITED Register - Bit Assignments % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ ______ ______ ______ ______ % % XX XX VIEWER VIEWER VIEWER VIEWER VIEWER VIEWER % % LIM-5 LIM-4 LIM-3 LIM-2 LIM-1 LIM-0 % % % % ************************************************************************* % % ** TUNE-DELAY Register - Bit Assignments % % D7 D6 D5 D4 D3 D2 D1 D0 % % ______ ______ ______ ______ _______ _______ _______ _______ % % XX XX XX XX DELAY-3 DELAY-2 DELAY-1 DELAY-0 % % % % % % ************************************************************************* % TITLE "Scam PLD Registers"; % RJF, 12/12/97 % % modified 2/4/98, RJF % % 2nd pass 3/6/98, RJF % % added TUN_DLY register & much-needed documentation, RJF, 5/8/98 % % added P-GUN Test mode & removed all Hall PSS statuses, RJF, 5/14/98 % % STILL MORE CHANGES TO COME, RJF, 5/18/98 % % updated veiwer-lim reg, removed unused Hall reg.s bits, RJF, 5/28/98 % % added ACC_MODE output for user-mode beam-sync generation by the Mizar % % RJF, 1/26/99 % % modifed register address mapping, reduced Harm. reg. width. RJF, 2/23/99 % % removed ACC_MODE selection of user-mode beam-sync generation by the Mizar % % added Harm register bit for selection of AC line_sync/Mizar user-mode % % beam-sync generation, RJF, 9/14/99 % % commented about HARMONIC bits 4 & 5, RJF, 01/12/06 %