% This subdesign inputs the 60Hz line-sync & generates 354-usec HI pulse	%
% (tune_beam) and a modulation signal (tun_mod), which are then sent on to	%
% the gun interface logic.							%
%										%
% 250-usec after the line-sync input occurs, an output pulse (tune_mod) is	%
% also generated.  This signal may be varied in width by controlling the	%
% value of a 4-bit register (tun_dly), which is described further in the	%
% SCAMREG section.  The output pulse-width ranges from 98.5-usec to		%
% 100.375-usec in 125-nsec increments.  The power-on default value of the	%
% register and the corresponding pulse-width is 99.5-usec.			%
%										%
% A state-machine is utilized to monitor and load an 11-bit counter	with	%
% the appropriate values during the beam-sync period. Decoding of the		%
% states is as follows:								%
%										%
%	s0: line_sync input "LO", wait for a "HI" input				%
%	s1: line_sync "HI", tun_beam "HI", tun_mod "LO", count 1st 125-usec	%
%	s2: tun_beam "HI", tun_mod "LO", count 2nd 125-usec			%
%	s3: tun_beam "HI", tun_mod "HI", count 98.4375-usec (98.5 - 1 clk)	%
%	s4: tun_beam "HI", tun_mod "HI", count  tun_dly, (( val. x 2) + 1 clk)	%
%	s5: tun_beam "HI", tun_mod "LO", count !tun_dly, ((!val. x 2) + 1 clk)	%
%	s6: tun_beam "HI", count 3.625-usec (final value to equal 354-usec)	%
%	s7: tun_beam "LO", wait for line_sync to be "LO"			%
%										%
% assuming a 100-usec modulation pulse is desired, the values would be:		%
% 	tun_beam = 354-usec (s1-s6), tun_mod = 100-usec (s3,s4)			%
%										%
%	   s0	(waiting for new line_sync)					%
%	   s1					125.0000 \			%
%	 + s2					125.0000 /  = (250-usec)	%
%	 + s3					 98.4375 \			%
%	 + s4	   val(12) x 2 + 62.5-ns  =	  1.5625 /  = (100-usec)	%
%	 + s5	  !val( 3) x 2 + 62.5-ns  =	  0.4375 \			%
%	 + s6					  3.5625 /  = (4-usec)		%
%	   s7	(no counting done)		  = 354.0000 usec		%
%										%
% The clock input (sysclk) is assumed to be 16MHz (62.5-nsec). Note that	%
% when entering states s3 and s4, bits 3-0 of the tun_dly register were		%
% loaded into bits 4-1 of the counter, providing a minimum step increment of	%
% 125-nsec.  Bits 10-5 of the counter are loaded with 0's.  Bit 0 is always	%
% loaded with a 1, ensuring a minimum stay of one clock-tick in each of the	%
% states regardless of the count value entered.					%
% The reset input (/sys_rst) ensures that the logic initializes properly.	%
% RJF, 1/29/98									%
% RJF, 5/4/98	REVISED, added tun_dly functionality				%
% RJF, 01/12/06  Updated routine with "constants"				%