[Halld-tracking-hw] fADC range (was FDC meeting minutes...)
Naomi Jarvis
nsj at cmu.edu
Tue Sep 21 11:21:24 EDT 2010
Thankyou for the explanation... Great! I'll look forward to getting the new fADC here soon.
Fernando, the 560mV is baseline to peak but I am still using the old cable (because we don't have the enough shaper channels connected to use the new one) so I'll switch to the new one for the new fADC; I will also have some software work to do for the extra 8 channels.
Thanks,
Naomi.
On Sep 21, 2010, at 10:49 AM, Fernando J. Barbosa wrote:
> Hi Gerard,
>
> I missed your email before I sent a reply to Naomi. My suggestion is to have the input range specified for real pulses out of the detectors, through the ASIC and 18 m of cable, add some margin and then use the fADC for validation. This is for one fADC assembly variant ("part number"). However, you may have a better plan to get the required information from the FDC and the CDC groups.
>
> I should remind everyone that our schedule shows production of the fADC125s starting in January. So, we need to work diligently on this.
>
> Best regards,
> Fernando
>
>
>
>
>
> Gerard Visser wrote:
>> Hi Naomi & all,
>> The shaper is amplifying the pulse height, yes. But this is all more complicated than people seem to be assuming. The shaper board, and the ADC125 module, have a _frequency dependent_ response. First there is the 'equalization filter' which ideally is set to cancel the roll-off in frequency response of the cable (but may be set differently, of course, for instance to also re-adjust some of the 'tail cancellation' filter which is in the ASIC). Second there is the shaping function itself, which squashes a tall skinny pulse into a shorter wider pulse, but leaves a slower input pulse unaffected.
>> So in short, you can't just specify 'the' input range of the ADC, and it is not a good idea to 'convert' the ADC scale into mV for analysis - better just leave it as the ADC scale. And any discussion about ADC input range needs to be in reference to some defined input pulse shape.
>> On a more practical note, Fernando and I are working to get one of the ADC boards to you at CMU soon. Then you can provide feedack to change the gain by a numerical factor, _that_ will be unambiguous. If it is decided to change the shaping time we need to do that first then finalize the gain factor, because for instance a shorter shaping time results in a need for lower gain factor so the skinny pulses don't get clipped.
>> Thanks,
>>
>> Gerard
>>
>> Naomi Jarvis wrote:
>>> Oh I am sorry, I did know that once, I must have misread the table.
>>>
>>> So... is the shaper in our current configuration also amplifying the pulse height? Does the 330mV from the preamp output at saturation correspond to our observed ~560mV shaper output?
>>>
>>> Would the new built-in shaping part of the new fADC also increase the pulse height, or can I just sum 330mV saturated preamp output + 50 mV pedestal and be confident that it will fit into 380mV new_fADC range ?
>>>
>>>
>>> Naomi.
>>>
>>>
>>>
>>> On Sep 20, 2010, at 4:24 PM, Fernando J. Barbosa wrote:
>>>
>>>> Hi Naomi,
>>>>
>>>> The dynamic range in GlueX-doc-1364 is at the input and in fC, not mV. For your configuration, the preamp differential output amplitude is 380 fC x 0.57 mV/fC = 216.6 mV (5% linearity).
>>>>
>>>> Best regards,
>>>> Fernando
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> Naomi Jarvis wrote:
>>>>> Hi Fernando and Gerard,
>>>>>
>>>>>
>>>>> We are very happy with the 550mV fADC range, preamp and HVB combination that we now have here at CMU. We were under the impression that the final fADC range was to be 0.5V.
>>>>> Gluex doc 1364 shows our preamp as having 380mV dynamic range; at that point it is 5% non-linear, saturation is very approximately 520mV.
>>>>> At present the pedestal requires ~25mV. I believe we can correct off-line for the preamp performance some way after passing the 5% non-linear mark at 380mV towards 520mV.
>>>>> Assuming the big CDC will initially be noisier, I would like to allow 50mV for its pedestal; then if this can be reduced we will have a happy increase in range.
>>>>>
>>>>> Would it be possible to give us a fADC range of 50mV (for pedestal) + 520mV preamp saturation point = 570mV?
>>>>>
>>>>> (Can you define the 520mV point more accurately? I obtained this from amplitude spectra, from the scope it looks more like 560mV.)
>>>>>
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Naomi.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> On Sep 17, 2010, at 12:13 PM, Curtis A. Meyer wrote:
>>>>>
>>>>>> Hi Fernando -
>>>>>>
>>>>>> We worked hard to get the dynamic range that we needed in the CDC and I am
>>>>>> not willing to give it up now. With regard to the peaking time, we have always stated
>>>>>> that in the CDC, we need 3-5 samples on the leading edge. This is 24-40ns rise time.
>>>>>> In the current setup, we have the shaper in front of the Flash ADC. We are under the
>>>>>> impression that this is built into the new flash ADC. That said, the 35ns peaking time
>>>>>> seems reasonable to us.
>>>>>>
>>>>>> Curtis
>>>>>> On 9/17/10 10:57 AM, Fernando J. Barbosa wrote:
>>>>>>> Hi Gerard and Lubomir,
>>>>>>>
>>>>>>> The peaking time with the preamp and 18 m of cable is 14 ns and so it is the minimum one can achieve. I agree that 25 ns would be the minimum in trying to get three samples on the leading edge for timing interpolation. On the other hand, a 35 ns peaking time is very reasonable so we are perhaps considering optimizing this between 25 ns and 35 ns and based on the benefits of noise shaping. I don't think Lubomir included the time walk correction but this can be found on GlueX-doc-1364 for the ASIC (GAS-II).
>>>>>>>
>>>>>>> Regarding the assembly variants, I agree with Eugene that we should try to get one fADC125 but we need to consider this carefully. We have considered two fADC125 assembly versions, one for the CDC (low gain preamp) and the other for the FDC strips (high gain preamp) primarily based on fully using the ADC dynamic range. The preamp output ranges (@ saturation) are not the same in the configurations we are using: 430 mV for high gain and 330 mV for low gain. If we set the ADC full scale (FS) at 430 mV (4095 on 12-bit), then 330 mV will be at 76% FS (3100 on 12-bit). Are we willing to sacrifice 25% of the ADC range on the CDC in exchange for one fADC125 version (based on saturation conditions)?
>>>>>>>
>>>>>>> However, there is another issue to consider if we are to have a single ADC. The output saturation at 430 mV is way out of the linear range and the output is 285 mV @ 5% linearity. For the CDC and the FDC:
>>>>>>>
>>>>>>> CDC - 330 mV @ Saturation, 207 mV @ 5% linearity
>>>>>>> FDC Strips - 430 mV @ Saturation, 285 mV @ 5% linearity
>>>>>>>
>>>>>>> For a single ADC solution, I propose we set the ADC FS at 380 mV. We can set this even lower for a tighter linear range of interest.
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Fernando
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Gerard Visser wrote:
>>>>>>>> Hi Lubomir,
>>>>>>>> We should perhaps discuss the shaping option ideas more fully in the next meeting, I can call in. I didn't realize this was on the agenda today.
>>>>>>>> In my opinion it is *feasible* to support two different versions of the module with different shaping time. This amounts only to different values for some capacitors, inductors, and resistors to be used in assembly. The quantities are large enough that there should be no significant cost impact, except for probably a larger overall quantity of spares to be built. Of course, I agree it is simpler to have only one version.
>>>>>>>> Presently the peaking time of the preamp-cable-ADC125 is about 35 ns I believe. (Maybe a bit more in the case of the cathodes if the detector capacitance affects it; it would make sense but I don't know really.) We might try to reduce it but 14 ns seems to me too small - there will be too much amplitude above the Nyquist zone, this has to degrade timing at some point. Maybe some compromise value like 25 ns would be better to try.
>>>>>>>> Anyway the starting point for this should probably be to remove all explicit shaping from a channel, hook it up w/ preamp and cable and a test pulser and input loading capacitor, and see the pulse shape. This will exhibit the minimum achievable peaking time; and we can also then we can calculate the shaping time for the ADC board to get to the desired overall peaking time.
>>>>>>>> Can you describe the algorithm applied to ADC data to get the timing measurement for page 514 work? Is there a fit here, or just level-crossing using the same threshold e.g. 30mV? Certainly an optimal timing algorithm will use more than 2 datapoints from the ADC, i.e., is not simply just a level crossing and linear interpolation between two points.
>>>>>>>> Is the discriminator simulation 'perfect' or does it include real-world distortions such as time walk (dispersion)?
>>>>>>>> Sincerely,
>>>>>>>>
>>>>>>>> Gerard
>>>>>>>>
>>>>>>>>
>>>>>>>> Lubomir Pentchev wrote:
>>>>>>>>
>>>>>>>>> The minutes of the last FDC meeting were posted at:
>>>>>>>>>
>>>>>>>>> http://www.jlab.org/Hall-D/software/wiki/index.php/Minutes-9-16-2010
>>>>>>>>>
>>>>>>>>> Regards,
>>>>>>>>> Lubomir
>>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> Halld-tracking-hw mailing list
>>>>>>>> Halld-tracking-hw at jlab.org
>>>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> Halld-tracking-hw mailing list
>>>>>>> Halld-tracking-hw at jlab.org
>>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>>>>
>>>>>> --
>>>>>> Prof. Curtis A. Meyer Department of Physics
>>>>>> Phone: (412) 268-2745 Carnegie Mellon University
>>>>>> Fax: (412) 681-0648 Pittsburgh PA 15213-3890 cmeyer at ernest.phys.cmu.edu http://www.curtismeyer.com/
>>>>>> _______________________________________________
>>>>>> Halld-tracking-hw mailing list
>>>>>> Halld-tracking-hw at jlab.org <mailto:Halld-tracking-hw at jlab.org>
>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>> <barbosa.vcf>
>>>
>>>
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>>> From: Naomi Jarvis <nsj at cmu.edu>
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>>>
>>> Oh I am sorry, I did know that once, I must have misread the table.
>>>
>>> So... is the shaper in our current configuration also amplifying the pulse height? Does the 330mV from the preamp output at saturation correspond to our observed ~560mV shaper output?
>>>
>>> Would the new built-in shaping part of the new fADC also increase the pulse height, or can I just sum 330mV saturated preamp output + 50 mV pedestal and be confident that it will fit into 380mV new_fADC range ?
>>>
>>>
>>> Naomi.
>>>
>>>
>>>
>>> On Sep 20, 2010, at 4:24 PM, Fernando J. Barbosa wrote:
>>>
>>>> Hi Naomi,
>>>>
>>>> The dynamic range in GlueX-doc-1364 is at the input and in fC, not mV. For your configuration, the preamp differential output amplitude is 380 fC x 0.57 mV/fC = 216.6 mV (5% linearity).
>>>>
>>>> Best regards,
>>>> Fernando
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> Naomi Jarvis wrote:
>>>>> Hi Fernando and Gerard,
>>>>>
>>>>>
>>>>> We are very happy with the 550mV fADC range, preamp and HVB combination that we now have here at CMU. We were under the impression that the final fADC range was to be 0.5V.
>>>>> Gluex doc 1364 shows our preamp as having 380mV dynamic range; at that point it is 5% non-linear, saturation is very approximately 520mV.
>>>>> At present the pedestal requires ~25mV. I believe we can correct off-line for the preamp performance some way after passing the 5% non-linear mark at 380mV towards 520mV.
>>>>> Assuming the big CDC will initially be noisier, I would like to allow 50mV for its pedestal; then if this can be reduced we will have a happy increase in range.
>>>>>
>>>>> Would it be possible to give us a fADC range of 50mV (for pedestal) + 520mV preamp saturation point = 570mV?
>>>>>
>>>>> (Can you define the 520mV point more accurately? I obtained this from amplitude spectra, from the scope it looks more like 560mV.)
>>>>>
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Naomi.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> On Sep 17, 2010, at 12:13 PM, Curtis A. Meyer wrote:
>>>>>
>>>>>> Hi Fernando -
>>>>>>
>>>>>> We worked hard to get the dynamic range that we needed in the CDC and I am
>>>>>> not willing to give it up now. With regard to the peaking time, we have always stated
>>>>>> that in the CDC, we need 3-5 samples on the leading edge. This is 24-40ns rise time.
>>>>>> In the current setup, we have the shaper in front of the Flash ADC. We are under the
>>>>>> impression that this is built into the new flash ADC. That said, the 35ns peaking time
>>>>>> seems reasonable to us.
>>>>>>
>>>>>> Curtis
>>>>>> On 9/17/10 10:57 AM, Fernando J. Barbosa wrote:
>>>>>>> Hi Gerard and Lubomir,
>>>>>>>
>>>>>>> The peaking time with the preamp and 18 m of cable is 14 ns and so it is the minimum one can achieve. I agree that 25 ns would be the minimum in trying to get three samples on the leading edge for timing interpolation. On the other hand, a 35 ns peaking time is very reasonable so we are perhaps considering optimizing this between 25 ns and 35 ns and based on the benefits of noise shaping. I don't think Lubomir included the time walk correction but this can be found on GlueX-doc-1364 for the ASIC (GAS-II).
>>>>>>>
>>>>>>> Regarding the assembly variants, I agree with Eugene that we should try to get one fADC125 but we need to consider this carefully. We have considered two fADC125 assembly versions, one for the CDC (low gain preamp) and the other for the FDC strips (high gain preamp) primarily based on fully using the ADC dynamic range. The preamp output ranges (@ saturation) are not the same in the configurations we are using: 430 mV for high gain and 330 mV for low gain. If we set the ADC full scale (FS) at 430 mV (4095 on 12-bit), then 330 mV will be at 76% FS (3100 on 12-bit). Are we willing to sacrifice 25% of the ADC range on the CDC in exchange for one fADC125 version (based on saturation conditions)?
>>>>>>>
>>>>>>> However, there is another issue to consider if we are to have a single ADC. The output saturation at 430 mV is way out of the linear range and the output is 285 mV @ 5% linearity. For the CDC and the FDC:
>>>>>>>
>>>>>>> CDC - 330 mV @ Saturation, 207 mV @ 5% linearity
>>>>>>> FDC Strips - 430 mV @ Saturation, 285 mV @ 5% linearity
>>>>>>>
>>>>>>> For a single ADC solution, I propose we set the ADC FS at 380 mV. We can set this even lower for a tighter linear range of interest.
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Fernando
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Gerard Visser wrote:
>>>>>>>> Hi Lubomir,
>>>>>>>> We should perhaps discuss the shaping option ideas more fully in the next meeting, I can call in. I didn't realize this was on the agenda today.
>>>>>>>> In my opinion it is *feasible* to support two different versions of the module with different shaping time. This amounts only to different values for some capacitors, inductors, and resistors to be used in assembly. The quantities are large enough that there should be no significant cost impact, except for probably a larger overall quantity of spares to be built. Of course, I agree it is simpler to have only one version.
>>>>>>>> Presently the peaking time of the preamp-cable-ADC125 is about 35 ns I believe. (Maybe a bit more in the case of the cathodes if the detector capacitance affects it; it would make sense but I don't know really.) We might try to reduce it but 14 ns seems to me too small - there will be too much amplitude above the Nyquist zone, this has to degrade timing at some point. Maybe some compromise value like 25 ns would be better to try.
>>>>>>>> Anyway the starting point for this should probably be to remove all explicit shaping from a channel, hook it up w/ preamp and cable and a test pulser and input loading capacitor, and see the pulse shape. This will exhibit the minimum achievable peaking time; and we can also then we can calculate the shaping time for the ADC board to get to the desired overall peaking time.
>>>>>>>> Can you describe the algorithm applied to ADC data to get the timing measurement for page 514 work? Is there a fit here, or just level-crossing using the same threshold e.g. 30mV? Certainly an optimal timing algorithm will use more than 2 datapoints from the ADC, i.e., is not simply just a level crossing and linear interpolation between two points.
>>>>>>>> Is the discriminator simulation 'perfect' or does it include real-world distortions such as time walk (dispersion)?
>>>>>>>> Sincerely,
>>>>>>>>
>>>>>>>> Gerard
>>>>>>>>
>>>>>>>>
>>>>>>>> Lubomir Pentchev wrote:
>>>>>>>>
>>>>>>>>> The minutes of the last FDC meeting were posted at:
>>>>>>>>>
>>>>>>>>> http://www.jlab.org/Hall-D/software/wiki/index.php/Minutes-9-16-2010
>>>>>>>>>
>>>>>>>>> Regards,
>>>>>>>>> Lubomir
>>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> Halld-tracking-hw mailing list
>>>>>>>> Halld-tracking-hw at jlab.org
>>>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> Halld-tracking-hw mailing list
>>>>>>> Halld-tracking-hw at jlab.org
>>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>>>>
>>>>>> --
>>>>>> Prof. Curtis A. Meyer Department of Physics
>>>>>> Phone: (412) 268-2745 Carnegie Mellon University
>>>>>> Fax: (412) 681-0648 Pittsburgh PA 15213-3890 cmeyer at ernest.phys.cmu.edu http://www.curtismeyer.com/
>>>>>> _______________________________________________
>>>>>> Halld-tracking-hw mailing list
>>>>>> Halld-tracking-hw at jlab.org <mailto:Halld-tracking-hw at jlab.org>
>>>>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
>>>> <barbosa.vcf>
>>>
>>>
>>> _______________________________________________
>>> Halld-tracking-hw mailing list
>>> Halld-tracking-hw at jlab.org
>>> https://mailman.jlab.org/mailman/listinfo/halld-tracking-hw
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