[Halld-tracking-hw] FADC125 meeting

[Fernando J Barbosa]

Hi David, all,

The document on the fADC125 data format specification is a bit vague but 
it is a good start to capture the requirements for the Hall D physics. 
Yesterday, we discussed some of the issues related to the on-board data 
processing, considering the fADC250 as a model. I realized that some 
information may not have been disseminated properly to serve as basis 
for further development. Ed and Hai will distribute a document soon 
outlining the data processing implemented on the fADC250 but here is a 
brief description on the subject of pedestals, based on my requested 
specifications, which have been discussed at length within the group 
over the last few years:

a) the fADC250 has zero suppression and pedestal subtraction.
b) the pedestal is subtracted from every sample within the integration 
window prior to processing
c) the pedestal value is maintained in a pedestal register
d) the pedestal value in the register is obtained by averaging n samples 
before the threshold was crossed OR by a value stored by the user (say, 
from a prior calibration run).

I agree that having the pedestal information available through the data 
stream may be used as a quality check.

I hope this clarifies some of the issues discussed yesterday.

Best regards,
Fernando






On 1/14/2014 10:53 AM, Naomi Jarvis wrote:
> Just a reminder that we have a meeting scheduled for this afternoon.
>
>
>> https://halldweb1.jlab.org/wiki/index.php/FADC_FPGA_Programming_Jan_14,_2014
>
>
>
> Regards,
>
> Naomi

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