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Hi Fernando -<br>
<br>
We worked hard to get the dynamic range that we needed in the CDC
and I am<br>
not willing to give it up now. With regard to the peaking time, we
have always stated <br>
that in the CDC, we need 3-5 samples on the leading edge. This is
24-40ns rise time.<br>
In the current setup, we have the shaper in front of the Flash ADC.
We are under the <br>
impression that this is built into the new flash ADC. That said, the
35ns peaking time<br>
seems reasonable to us.<br>
<br>
Curtis<br>
On 9/17/10 10:57 AM, Fernando J. Barbosa wrote:
<blockquote cite="mid:4C9381C8.9040200@jlab.org" type="cite">Hi
Gerard and Lubomir,
<br>
<br>
The peaking time with the preamp and 18 m of cable is 14 ns and so
it is the minimum one can achieve. I agree that 25 ns would be the
minimum in trying to get three samples on the leading edge for
timing interpolation. On the other hand, a 35 ns peaking time is
very reasonable so we are perhaps considering optimizing this
between 25 ns and 35 ns and based on the benefits of noise
shaping. I don't think Lubomir included the time walk correction
but this can be found on GlueX-doc-1364 for the ASIC (GAS-II).
<br>
<br>
Regarding the assembly variants, I agree with Eugene that we
should try to get one fADC125 but we need to consider this
carefully. We have considered two fADC125 assembly versions, one
for the CDC (low gain preamp) and the other for the FDC strips
(high gain preamp) primarily based on fully using the ADC dynamic
range. The preamp output ranges (@ saturation) are not the same in
the configurations we are using: 430 mV for high gain and 330 mV
for low gain. If we set the ADC full scale (FS) at 430 mV (4095 on
12-bit), then 330 mV will be at 76% FS (3100 on 12-bit). Are we
willing to sacrifice 25% of the ADC range on the CDC in exchange
for one fADC125 version (based on saturation conditions)?
<br>
<br>
However, there is another issue to consider if we are to have a
single ADC. The output saturation at 430 mV is way out of the
linear range and the output is 285 mV @ 5% linearity. For the CDC
and the FDC:
<br>
<br>
CDC - 330 mV @ Saturation, 207 mV @ 5% linearity
<br>
FDC Strips - 430 mV @ Saturation, 285 mV @ 5% linearity
<br>
<br>
For a single ADC solution, I propose we set the ADC FS at 380 mV.
We can set this even lower for a tighter linear range of interest.
<br>
<br>
Best regards,
<br>
Fernando
<br>
<br>
<br>
<br>
<br>
<br>
Gerard Visser wrote:
<br>
<blockquote type="cite">Hi Lubomir,
<br>
We should perhaps discuss the shaping option ideas more
fully in the next meeting, I can call in. I didn't realize this
was on the agenda today.
<br>
In my opinion it is *feasible* to support two different
versions of the module with different shaping time. This amounts
only to different values for some capacitors, inductors, and
resistors to be used in assembly. The quantities are large
enough that there should be no significant cost impact, except
for probably a larger overall quantity of spares to be built. Of
course, I agree it is simpler to have only one version.
<br>
Presently the peaking time of the preamp-cable-ADC125 is
about 35 ns I believe. (Maybe a bit more in the case of the
cathodes if the detector capacitance affects it; it would make
sense but I don't know really.) We might try to reduce it but 14
ns seems to me too small - there will be too much amplitude
above the Nyquist zone, this has to degrade timing at some
point. Maybe some compromise value like 25 ns would be better to
try.
<br>
Anyway the starting point for this should probably be to
remove all explicit shaping from a channel, hook it up w/ preamp
and cable and a test pulser and input loading capacitor, and see
the pulse shape. This will exhibit the minimum achievable
peaking time; and we can also then we can calculate the shaping
time for the ADC board to get to the desired overall peaking
time.
<br>
Can you describe the algorithm applied to ADC data to get
the timing measurement for page 514 work? Is there a fit here,
or just level-crossing using the same threshold e.g. 30mV?
Certainly an optimal timing algorithm will use more than 2
datapoints from the ADC, i.e., is not simply just a level
crossing and linear interpolation between two points.
<br>
Is the discriminator simulation 'perfect' or does it include
real-world distortions such as time walk (dispersion)?
<br>
Sincerely,
<br>
<br>
Gerard
<br>
<br>
<br>
Lubomir Pentchev wrote:
<br>
<blockquote type="cite">The minutes of the last FDC meeting were
posted at:
<br>
<br>
<a class="moz-txt-link-freetext" href="http://www.jlab.org/Hall-D/software/wiki/index.php/Minutes-9-16-2010">http://www.jlab.org/Hall-D/software/wiki/index.php/Minutes-9-16-2010</a>
<br>
<br>
Regards,
<br>
Lubomir
<br>
</blockquote>
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<pre class="moz-signature" cols="72">--
Prof. Curtis A. Meyer Department of Physics
Phone: (412) 268-2745 Carnegie Mellon University
Fax: (412) 681-0648 Pittsburgh PA 15213-3890
<a class="moz-txt-link-abbreviated" href="mailto:cmeyer@ernest.phys.cmu.edu">cmeyer@ernest.phys.cmu.edu</a> <a class="moz-txt-link-freetext" href="http://www.curtismeyer.com/">http://www.curtismeyer.com/</a>
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