[Vetroc_daq_sbs] HV calibration

[Carlos Ayerbe]

Hi all, 

after yesterday Bogdan checking of the pedestals and a few suggestions, I think I can propose this prototype set-up to be used with VETROC.

Attached is the ADC plot of the 80 PMTs with the HV modified in order to have the SPE peak around 30ch over pedestal. The acquisition gate was reduced from 120 ns to 74 ns. The LED voltage was reduced from 3.6 to 3.5V. 

Those lousy channels... I'll check as soon as possible. 

I didn't test this set-up with the VETROC (thus the NINO thresholds), so I guess this can go as soon Evan give green light. 

Comments? Suggestions? 

Thank you

-Carlos


-------------- next part --------------
A non-text attachment was scrubbed...
Name: SPE_30ch.pdf
Type: application/pdf
Size: 183826 bytes
Desc: not available
URL: <https://mailman.jlab.org/pipermail/vetroc_daq_sbs/attachments/20161118/426451db/attachment-0001.pdf>