[Vetroc_daq_sbs] Understanding the trigger timing

[R. Evan McClellan]

Hey Ben,

We'd like to clarify our understanding of the behavior of the trigger signal in the current GRINCH DAQ prototype setup.

Here is my understanding:
-the PMT and reference channel signals go into the VETROC, and are stored in a pipeline
-the GTP reads the VETROC pipeline memory directly, through the back-plane, and makes a trigger decision
-the trigger signal is sent out from the front of the GTP, passes through the VETROC (for LVDS->ECL conversion), and then goes into the TI
-after the TI receives the trigger signal, it stops and reads out the VETROC through the back-plane

We did a quick test to check this understanding. We significantly reduced the length of the cable carrying the trigger signal from the GTP to the VETROC.
We expected to see the timing of the reference channel TDC hits shift (due to the TI stopping the VETROC TDC earlier). However, the timing remained exactly the same.

Where is the mistake in our understanding?

Thanks!
Evan


R. Evan McClellan, PhD
Hall A Postdoctoral Fellow
Jefferson Lab