[Dsg-hallb_magnets] Questions regarding digital filter for Hall B Magnet Fast-Daq

[Nicholas Sandoval]

Hi Tyler,

1.  The noise is the same on all voltage taps, the problem arises when we multiply the noise for the scaled channels.  The fix should be implemented on all channels so as to keep the timing the same.  

2.  Some of the voltage taps are scaled due to the nature of the magnet.  The coils see much larger overall voltage so the settings on the iso-amp are configures such that we can see the full scale.  This requires us to rescale on the software side to get a 1 to 1 ratio. 

3.  We performed testing of the iso-amps installed in the hall and in my laboratory, both instances the output was very similar and less than the manufacturers specification.  ~10mv RMS(spec), I see about 6mV on the O-scope for our installation and in the lab

4.  Currently the interlock trips @ 600mS after staying over the threshold(three samples).  But, this is subject to change and has changes several times

5.  The logged data is available through the fast daq viewer on the EPICs gui.  It is also stored in ROOT. 60Hz is the noise we are most interested in removing.

If you would like please set up a meeting this morning or this afternoon and we can go though the data in more detail, and also I can show you how to access the root files if needed.

Best Regards,

Nick
----- Original Message -----
From: "Tyler Lemon" <tlemon at jlab.org>
To: "dsg-hallb magnets" <dsg-hallb_magnets at jlab.org>
Sent: Thursday, January 12, 2017 10:10:32 AM
Subject: [Dsg-hallb_magnets] Questions regarding digital filter for Hall B	Magnet Fast-Daq

Hello Ruben and Renuka, 

I have been investigating how to add digital filters to the Fast-Daq programs and have the following questions: 


    1. Are there noise issues on all voltage taps or just the ones that are being scaled? 
    2. Why are some voltage taps scaled while others are not? 
    3. Is there documentation for the iso-amps' grounding scheme? 
        1. Looking at Solenoid drawing B00000-09-0683 for how the voltage taps are wired to the iso-amp and then to the cRIO, there is no indication that the iso-amps are grounded. 
    4. How fast should the interlock trip after a voltage spike? 
    5. Is there logged data of the voltage tap noise? 
        1. For the filter, it would help to know if the noise is of a constant frequency or just white noise. 

In regards to applying and testing a filter in LabVIEW, there is a version of the Fast-Daq cRIO FPGA code almost ready for testing with lowpass filters applied to only the channels that are scaled. However, before testing this code, it would be good to have the above questions answered. 

Best regards, 
Tyler 


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