[Dsg-rich] Question on RICH FPGA temperature soft interlocks

[Tyler Lemon]

Hi Nathan, 

Yesterday, there was a soft interlock trip on RICH FPGA temperature caused by a data read out error (temperature did not actually go over limit). 

In the archiver, we can see that LV turned off when the temperature jumped over the threshold. However, there were two similar temperature spikes on the FPGA temperature a few minutes before the interlock actually tripped where LV was not disabled. 

Is there any sort of trip delay or time-over-threshold for the soft interlock that would explain why the interlock did not trip LV off on the first two spikes? 

Best regards, 
Tyler 
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