[Dsg-rich] RICH airflow tests?

[Tyler Lemon]

Hello Marco and Valery, 

A few months ago, you mentioned that it'd be good to figure out more precisely what airflow is needed to keep RICH electronics cool. 

Since there will not be beam and Hall B will be open until next week, would we be able to run tests this week to determine how changes in cooling airflow affect RICH FPGA temperatures and hardware interlock RTDs? 

The general procedure in the study would be: 
1.) turn on HV/LV and let the EP reach its normal running temperature. 
2..) decrease airflow to set values (decrease in ~50 slm increments?). 
3.) Allow RICH to reach a steady temperature after change. 
4.) Repeat steps 2 and 3 until FPGA temperatures reach some upper limit (maybe 75 deg C?) 

The tests would also allow better limits on the hardware interlock to be set because we would have data supporting at what airflow RICH electronics temperatures start to get too high. 

Please let us know. 

Best regards, 
Tyler 
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