[Dsg-rich] RICH recovery

[Benjamin Raydo]

Hi Tyler,


There are no known limitations to the number of times the equipment can be power cycled. I think the life expectancy of the RICH FPGA modules will be determined from the amount of time powered and/or in the beam, but not related to the number of power cycles (there's nothing abusive about the power up sequencing compared to normal running).


If DAQ downtime due to RICH becomes a problem we can look into some improving it's behavior, but a big issue for the moment. That said, anybody that has time and/or interest in making the software/firmware more robust is welcome to look at it and we can help you get setup to try it out. Eventually another sector will show up and make for twice the issues!


Ben

________________________________
From: Dsg-rich <dsg-rich-bounces at jlab.org> on behalf of Tyler Lemon <tlemon at jlab.org>
Sent: Tuesday, February 19, 2019 2:18:19 PM
To: dsg-rich
Subject: [Dsg-rich] RICH recovery


Hello,


We have noticed that regularly (almost on a daily basis) that the RICH recovery procedure is used.


Previously, Valery has told us that the recovery procedure does the following:

  1.  LV off
  2.  LV on
  3.  ssh rich4
  4.  rich_init


With the frequency of reboots of RICH DAQ, we are concerned that the reboots will lower the lifespan of the MAPMTs and readout electronics. How many times could the system be reinitialized without the chance of failure?


Best regards,

Tyler
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