[Dsg-rich] [EXTERNAL] meeting with DSG

[Marco Mirazita]

Hi Ben, Brian,
as far as I know, only one of the 3 monitored temperatures is recorded 
in epics.
However, all of them are recorded during the scaler data taking (when 
the slow control is disabled) in a text file that is continuously 
updated. You can see this file here:
/home/clasrun/rich/suite1.0/data/temperature/ssprich_Temperatures.txt
The tiles are identified here by slot and channel, the tile 128 (the hot 
one) is slot 7 channel 12.
These data actually show that for some FPGA the 3 temperatures are close 
each other, but for some other FPGA the differences are up to 5 or 6 
degrees.
As for the calibration, I attached here the same data we were looking at 
today, but sampled every 10 seconds instead of 1 minute. We see that 
tile 128 starts a bit higher than the others (for example tile 127) but 
then the difference increases with time. Therefore, I would say that 
tile 128 is hotter partly because of calibration, partly because it 
produces more heat.
A way to minimize the impact of possible miscalibration could be to send 
to epics display and interlocks the average of the three values. Would 
this be possible?
Best regards,
Marco



Il 2019-10-14 16:47 Benjamin Raydo ha scritto:
> Hi Brian,
> 
>  Right, we're monitoring the FPGA internal temp sensor using the XADC.
> 
> 
>  I don't know what the original question was, but wanted to mention
> that we have two more temperatures monitored in the external
> regulators (which was the XADC analog-to-digital converter) - they are
> in EPICS, but I'm not sure if they are archived.
> 
>  Also, I would expect it's possible to cross-check or calibrate the
> temperature sensors if one monitors the temperature as the system
> turns on - you should be able extrapolate to the box temperature
> before it was powered and see how well everything agrees.
> 
>  Ben
> 
>  From: Brian Eng
> 
>  Sent: Monday, October 14, 10:17 AM
> 
>  Subject: Re: [Dsg-rich] [EXTERNAL] meeting with DSG
> 
>  To: marco mirazita
> 
>  Cc: dsg-rich at jlab.org
> 
>  Hi Marco,
> 
>  Regarding the FPGA temperatures, since we don't have the FPGA code
> itself we can only make an educated guess, but it's quite likely that
> it is using the on-die temperature sensor.
> 
>  
> https://urldefense.proofpoint.com/v2/url?u=https-3A__www.xilinx.com_support_documentation_user-5Fguides_ug480-5F7Series-5FXADC.pdf&d=DwICAg&c=CJqEzB1piLOyyvZjb8YUQw&r=sLmN_kLNB8f_QBCYTgZaO1cK1zcpXSUHz0BQf_04bYk&m=S3A8nxmZyDupn4_w1hoP8BsSbXppost9twT7sAZkhKM&s=YrFbkxyAy4dwNSTFyo4NIoeYcKf-vCtjT-8FSzDsrZ0&e= 
> [1]
> 
>  (page 14, figure 1-1)
> 
>  Note that this sensor has an error of +/- 4C when the temp is < 100C
> 
>  > On Oct 14, 2019, at 3:35 AM, mirazita at jlab.org wrote:
> 
>  >
> 
>  >
> 
>  > marco mirazita has invited you to a meeting.
> 
>  _______________________________________________
> 
>  Dsg-rich mailing list
> 
>  Dsg-rich at jlab.org
> 
>  https://mailman.jlab.org/mailman/listinfo/dsg-rich [2]
> 
> 
> 
> Links:
> ------
> [1]
> https://urldefense.proofpoint.com/v2/url?u=https-3A__www.xilinx.com_support_documentation_user-5Fguides_ug480-5F7Series-5FXADC.pdf&d=DwICAg&c=CJqEzB1piLOyyvZjb8YUQw&r=sLmN_kLNB8f_QBCYTgZaO1cK1zcpXSUHz0BQf_04bYk&m=S3A8nxmZyDupn4_w1hoP8BsSbXppost9twT7sAZkhKM&s=YrFbkxyAy4dwNSTFyo4NIoeYcKf-vCtjT-8FSzDsrZ0&e= 
> [2] https://mailman.jlab.org/mailman/listinfo/dsg-rich
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