[Dsg-rich] [EXTERNAL] RICH electronics

Mon Sep 23 17:33:39 EDT 2019

Hi Tyler,

Matteo is correct about the temperature limit of 85C to respect the FPGA timing constraints, but we also have fiber cables running close to those parts that are rated for 80C (I'd expect some deformation possible if we go above this for a long period).

Can we set a safe limit of 75C for any reported FPGA temperature for your tests (short term limit: <1hr)? If your tests need to run in such a way that you want a higher limit, let us discuss again if you don't mind. For long term it would be great to keep it as low as possible and for the moment I believe we've been running with the hottest FPGA temp to be around 65C so don't want to see that increase significantly if there are any changes to the cooling.

Hope that helps.

Thanks,
Ben
________________________________
From: Tyler Lemon <tlemon at jlab.org>
Sent: Monday, September 23, 2019 4:59 PM
To: Amrit Yegneswaran <yeg at jlab.org>; Marco Mirazita <Marco.Mirazita at lnf.infn.it>; Benjamin Raydo <braydo at jlab.org>
Cc: dsg-rich <dsg-rich at jlab.org>
Subject: Re: [Dsg-rich] [EXTERNAL] RICH electronics

Hi Ben,

In October, we're planning on doing some testing to optimize RICH's cooling system and see what would needed to modify the system to cool two RICH sectors.

With respect to the RICH readout electronics, FPGAs, and their timing, are there any temperature limits we should take into consideration when testing the cooling system?

Thanks,
Tyler
________________________________
From: Amrit Yegneswaran <yeg at jlab.org>
Sent: Monday, September 23, 2019 4:48 PM
To: Tyler Lemon <tlemon at jlab.org>; Marco Mirazita <Marco.Mirazita at lnf.infn.it>
Cc: dsg-rich <dsg-rich at jlab.org>
Subject: Re: [Dsg-rich] [EXTERNAL] RICH electronics

tyler
address fpga temp issue with ben.
i believe 60c is right at the edge of timing issues, not sure.
________________________________
From: Dsg-rich <dsg-rich-bounces at jlab.org> on behalf of Tyler Lemon <tlemon at jlab.org>
Sent: Monday, September 23, 2019 3:11 PM
To: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
Cc: dsg-rich <dsg-rich at jlab.org>
Subject: Re: [Dsg-rich] [EXTERNAL] RICH electronics

Hi Marco,

Looking back at EP temperatures during steady operations (I picked 3/10/2019 to 3/31/2019), Hardware Interlock RTDs were ~40 deg C and FPGA temperatures were ~60 deg C.

Is there a temperature increase that would be considered acceptable? For example if the FPGA temperatures were ~70 deg C rather than ~60 deg C?

The first test should be determining what flow rate is actually needed to maintain EP temperatures in that acceptable range with all RICH electronics on.

-Tyler

________________________________
From: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
Sent: Monday, September 23, 2019 9:01 AM
To: Tyler Lemon <tlemon at jlab.org>
Cc: dsg-rich <dsg-rich at jlab.org>
Subject: Re: [Dsg-rich] [EXTERNAL] RICH electronics

Hi Tyler,
sorry, I had in mind that the replacement of the PT was scheduled for
last Wednesday.

The tests we have in mind to optimize the cooling system is basically
what you said. But we still have to make a plan of the specific
measurements we need. We will do this plan in the next weeks.
Any suggestion from you and the DSG is welcome.

Best regards,
Marco

Il 2019-09-20 20:46 Tyler Lemon ha scritto:
> Hi Marco,
>
>  The PT replacement has not been completed. It is scheduled for next
> Wednesday September 25.
>
>  As for the visit to optimize RICH running conditions, I will not be
> at work for at least part of the week of October 21 to October 25,
> however there should be other people from DSG that would be able to
> help.
>
>  What tests are being planned for the visit? Would it essentially be
> varying the settings of the cooling system (flow rate, buffer tank
> pressure, compressor output pressure) and seeing how the temperature
> within RICH is affected?
>
>  Best regards,
>  Tyler
>
> -------------------------
>
> FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>  SENT: Friday, September 20, 2019 12:21 PM
>  TO: Tyler Lemon <tlemon at jlab.org>
>  CC: dsg-rich <dsg-rich at jlab.org>; Valery Kubarovsky <vpk at jlab.org>;
> marco contalbrigo <mcontalb at fe.infn.it>
>  SUBJECT: Re: [EXTERNAL] RICH electronics
>
> Hi Tyler,
>  do you know if Bob has completed the replacement of the FT?
>  If so, the compressor could be restarted on Monday morning, once we
> are
>  sure everything is working properly I can turn on the RICH
> electronics
>  and keep it on for the night and then make the tests on Tuesday
> morning.
>
>  As you know, we didn't have much time to optimize the working point
> of
>  the cooling system after the RICH installation, we simply choose
> running
>  conditions that ensure a safe operation of the detector.
>  But these running conditions might be problematic with two RICH
> modules
>  and definitely not sustainable in case of failure of one of the two
>  compressors.
>  Therefore, also in preparation of the upcoming CLAS12 data taking,
> I'm
>  planning a visit to JLab for Dario and Sandro to try to optimize the
>  running conditions, and to be effective this work must be coordinated
>
>  with you and the DSG.
>  The proposed dates are from October 21 to October 31. Is this plan ok
>
>  for you?
>  Thank you,
>  Marco
>
>  Il 2019-09-18 14:12 Tyler Lemon ha scritto:
>  > Hi Marco,
>  >
>  > Bob Miller has scheduled the replacement of the faulty pressure
>  > transducer (PT) on the air-cooling buffer tank for next Wednesday,
>  > September 25.
>  >
>  > Could the tests be scheduled to start Thursday September 26?
>  >
>  > Best regards,
>  > Tyler
>  >
>  > -------------------------
>  >
>  > FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>  > SENT: Wednesday, September 18, 2019 4:08 AM
>  > TO: Tyler Lemon <tlemon at jlab.org>
>  > CC: dsg-rich <dsg-rich at jlab.org>; Valery Kubarovsky <vpk at jlab.org>;
>  > marco contalbrigo <mcontalb at fe.infn.it>
>  > SUBJECT: [EXTERNAL] RICH electronics
>  >
>  > Hi Tyler,
>  > the RICH electronics is off since quite a lot of time and in
>  > preparation
>  > of the upcoming CLAS12 running I would like to turn it on to verify
>  > that
>  > everything is still working and eventually to take new scaler
>  > calibration data.
>  > I could plan this work for the beginning of the next week.
>  > In preparation for that, we should coordinate to have all the
> systems
>  >
>  > ready. Would you be available to start the compressor for the test?
>  > Thank you,
>  > Marco
>
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