[dsg-svt] SVT outinhibit

[Peter Bonneau]

The Hardware Interlock trip latch is only reporting the low coolant flow 
event at 20:27 and therefore should not have disabled the Mpod crate 
controller before this event.

To check the Mpod crate controller and the interlock disable signal:

1) To check the hardware interlock Mpod logic, you can try disabling the 
inlet and outlet coolant flow interlock enables. After disabling and at 
the next trip event, take screen captures of the "Interlock Status and 
signal monitoring" and the "Raw data monitoring" tabs of the Hardware 
Interlock Monitoring System user interface.

2) To check the Mpod crate controller input inhibit signal, you can try 
turning on the Mpod interlock system override key switch on the cRio 
crate. This effectively shorts all the Mpod crate enables to the +5V 
supply.

The crate enable signals share the +5V supply with the humidity sensors. 
To check the stability of this supply at the time of the last trip, I 
looked at the humidity signals shown in the attached EPICS Mya archive 
chart. If the +5V was unstable at the time of the trip event, there 
would be a large fluctuation in the humidity measurements. No 
fluctuations were seen at the time of the trip.



On 10/16/2017 2:05 PM, Yuri Gotra wrote:
>
> Thank you Peter,
>
> I still see the same picture as it was last week, see the attached 
> picture: HV R1:outinhibit was first (20:04), then fast powering off HV 
> and LV, then (because the heat source, LV, was removed) temperature 
> gradually decreased till (as designed) the ambient temperature soft 
> interlock stopped the chiller (20:27).
>
> The question is why R1 HV outinhibit was issued. Please let me know 
> your suggestions on further debugging. Thank you
>
>
> On 10/16/17 11:21 AM, Peter Bonneau wrote:
>> We had another trip of the SVT on 10/15/2017 at 20:27.
>>
>> Analysis of the trip for the Hardware Interlock System showed that 
>> low coolant flow was detected followed by the shutdown of all low and 
>> high voltage. This is the correct response for the interlock system. 
>> The interlock system can not stop coolant flow.
>>
>> As shown in the attached EPICS Mya archive chart, a slow rise in 
>> coolant temperature occurred after the trip.
>>
>>
>> Peter
>>
>>
>> ------------------------------------------------------------------------
>> *From: *"Peter Bonneau" <bonneau at jlab.org>
>> *To: *"Yuri Gotra" <gotra at jlab.org>, dsg-svt at jlab.org
>> *Sent: *Friday, October 13, 2017 7:38:36 AM
>> *Subject: *Re: SVT outinhibit
>>
>> Yuri:
>>
>> I checked on the hardware interlock system system this morning and it's
>> running normally (no trips overnight).
>>
>> After a system trip and before resetting, we need screen captures of the
>> "Interlock Status and signal monitoring" and the "Raw data monitoring"
>> tabs of the Hardware Interlock Monitoring System user interface for
>> troubleshooting. We need to know which signal is causing the tripping.
>>
>> The last time we had an issue like this (1/31/2017) ,  the problem was
>> caused by a loose connection to the  external coolant system monitoring
>> electronics  (Proteus Industries sensor and Florite 990x Controller.)
>>
>> As mentioned back in January, we don't have spares for the external
>> coolant monitoring electronics. I recommend we purchase spares for this
>> system.
>>
>> Peter
>>
>> On 10/12/2017 8:31 PM, Yuri Gotra wrote:
>> > Dear Peter,
>> >
>> > We had another crate inhibit issue this evening. Software interlocks
>> > were ok, chiller running.
>> >
>> > HV inhibit was red and all HV channel inhibits had errors. HV and LV
>> > ramped down.
>> >
>> > On the screenshot you could see B_SVT_HV_R1:outinhibit major
>> > HIHI_alarm at 20:06.
>> >
>> > Please let us know your suggestions on debugging this issue. Thank you
>> >
>

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