[dsg-svt] [New Logentry] Low Voltage (VDDA) Current Draw

[beng at jlab.org]

Logentry Text:
--
Tests were done comparing the regulator voltage output on VDDA and module current draw using P54 from the 8 module test stand in EEL/124.

A register test was done first at the nominal voltage to initialize all the chips then voltage was measured at the L1C using the pads of L1 (top pad = regulator out, bottom pad = L1C input). The middle pin of J5 was used for the ground reference. Voltage was measured with a Keithley 2002, current was from the isegSnmpControl GUI program.

Only top VDDA was changed, all other voltages were left at their nominal values (3.25V for LV and 85V for HV)

After the voltage/current measurements were taken register tests were done at a few different values. Pass = both chips had no errors, mixed = one chip had a failure (usually U1), and fail = both chips had errors.

---

This is a plain text email for clients that cannot display HTML.  The full logentry can be found online at https://logbooks.jlab.org/entry/3544082
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://mailman.jlab.org/pipermail/dsg-svt/attachments/20180309/5e389d75/attachment-0001.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: LV VDDA Current Draw.png
Type: image/png
Size: 73941 bytes
Desc: not available
URL: <https://mailman.jlab.org/pipermail/dsg-svt/attachments/20180309/5e389d75/attachment-0001.png>