[dsg-hallb_svt] Debugging SVT DAQ

[Brian Eng]

Hi Yuri,

I'm still on vacation but trying to catch up on emails, I'll try and troubleshoot R1 M2 some more on Monday night. There isn't really any pins specifically for registers 17 & 18 so it's a bit concerning that only those are failing. It's just shift in, shift control, shift out and the bco clock lines to read the registers, but those are shared among all the chips on a module. So it being a bad cable or connector if 3/4 of the chips pass 100% and 1/4 chips pass on all but 2 registers would be strange indeed.

For the MVT cables, is help still needed there? If so is there some sort of procedure that someone could follow or is it just a visual inspection of the cables? For the labeling do we need to provide the supplies or are they already on-site? Is there a naming scheme to follow for them?

________________________________
From: dsg-hallb_svt <dsg-hallb_svt-bounces at jlab.org> on behalf of Yuri Gotra <gotra at jlab.org>
Sent: Thursday, April 22, 2021 10:40 AM
To: Marco Battaglieri <battagli at jlab.org>
Cc: dsg-hallb_svt at jlab.org <dsg-hallb_svt at jlab.org>
Subject: [dsg-hallb_svt] Debugging SVT DAQ


Dear Marco,

We need Brian's expertise in debugging the SVT DAQ issue we need to resolve. We did not get feedback about his availability for this task. SVT integration will be on hold for now, we continue with BMT integration.
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