[dsg-hallb_svt] Debugging SVT DAQ

[Yuri Gotra]

Hello Brian,


Thank you for your help. Since DSG could not help us, labeling the 
cables we shared between Armen, Rafayel, and myself. It took some time 
from our workflow but we survived :-). We already integrated one of the 
3 BMT sectors, connected the cables and all the pedestals are good.

What I saw was all 4 chips of SVT R1S2 failed the same way. The weird 
thing is that first time they failed on Monday, nobody touched the SVT 
during the w/e and they were good on previous Friday. It would be great 
if you could help us with debugging, you knowledge of the FSSR2 chip is 
essential for this task. Once the issue is understoold and solved, we 
will proceed with connection region 2.


On 4/23/21 11:06 AM, Brian Eng wrote:
> Hi Yuri,
>
> I'm still on vacation but trying to catch up on emails, I'll try and 
> troubleshoot R1 M2 some more on Monday night. There isn't really any 
> pins specifically for registers 17 & 18 so it's a bit concerning that 
> only those are failing. It's just shift in, shift control, shift out 
> and the bco clock lines to read the registers, but those are shared 
> among all the chips on a module. So it being a bad cable or connector 
> if 3/4 of the chips pass 100% and 1/4 chips pass on all but 2 
> registers would be strange indeed.
>
> For the MVT cables, is help still needed there? If so is there some 
> sort of procedure that someone could follow or is it just a visual 
> inspection of the cables? For the labeling do we need to provide the 
> supplies or are they already on-site? Is there a naming scheme to 
> follow for them?
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