[Dsg-hallc_controls] Revised routine

[Amanda Hoebel]

Hi Mike, 

Attached are the PDFs of the revised function block diagrams and ladder logic. 

Regards, 
Amanda 



From: "Mike Fowler" <fowler at jlab.org> 
To: "dsg-hallc controls" <dsg-hallc_controls at jlab.org> 
Sent: Monday, November 12, 2018 8:43:23 AM 
Subject: Re: [Dsg-hallc_controls] DSG's PLC tasks report 

>>>DSG's weekly report 
>>>Modified to PLC routine to ramp down the quadrupoles when interlock is enabled 
(PSU_Sum_Interlock bit =1). 
Not required. The existing PLC code ramps down the power supply when there is an interlock. 

>>>>Added pulse-timer that waits for 100 ms and then transmits trigger pulse to enable the sending of 
0 A current value. 
Not required. 

The new current regulation code should go into standby waiting for new input. 
The code should not try to control the power supply when/if there is an interlock. 

Cheers, 
Mike 




On 11/9/2018 4:56 PM, Pablo Campero wrote: 



Hello, 

I have attached the DSG's weekly report for Hall C-PLC tasks. 

Best Regards, 
Pablo 


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