[G12] g12 triggers

[Andrea Celentano]

Hi Ben,
thanks! Concerning this bit 8, in the file:

/usr/clas/parms/trigger/config/g12/g12_LUT_L2_102212.cfg (that should be the “good” one used in g12), in line 145 I see that bit8 (at level1) was disabled. All the others were enabled.

Concerning the single sector, in the file:

/usr/clas/parms/trigger/config/g12/g12_LUT_single_sector.cfg

in the line 144 I see that bits 7,8,9 were disabled.

Therefore, maybe what I see in the data files is ok (unless disabled means that they’re still reported in the output bank but not enabled to trigger readout).

Thanks 

Andrea

> On Feb 18, 2019, at 17:03, Benjamin Raydo <braydo at jlab.org> wrote:
> 
> Hi Andrea,
> 
> I'll have a chance to look at this with Sergey & Valery this week. I have some guesses, but need to dig into more details to refresh my memory on this first.
> 
> Thanks,
> Ben
> From: Andrea Celentano <andrea.celentano at ge.infn.it>
> Sent: Monday, February 18, 2019 10:46:04 AM
> To: g12
> Cc: Sergey Boyarinov; Benjamin Raydo
> Subject: Re: g12 triggers
>  
> Dear g12,
> had anyone any change to look at this? Furthermore, I see other inconsistencies in the g12 trig table (table 3 in the note). For example, I never see trigger bit 8, that a part from L2, should be the same as trigger bit 1.
> I see this effect also in MK thesis (fig. 93 pag 140) - trigger bit 2 is ON for some events, while trigger bit 8 is always OFF.
> 
> Thanks
> Andrea
> 
>> On Feb 14, 2019, at 16:49, Andrea Celentano <andrea.celentano at ge.infn.it <mailto:andrea.celentano at ge.infn.it>> wrote:
>> 
>> Dear g12,
>> I am looking at the trigger efficiency of trigger bit #5 (STxTOF x (ECPx2)). 
>> 
>> Before doing so, I wanted to do some checks on the way trigger bits were reported in the output banks. 
>> I have taken from tape a single file from run 56541 (file A00), and I opened it via bosdump, printing HEAD, TGBI and RC26 banks.
>> 
>> According to g12 note (table 2 pag. 5), for this run trigger bits 1..6 are MORA x (STxTOF)_i x (STxTOF), without any prescale and without L2.
>> Trigger bit 8 is MORA x (STxTOF)x2.
>> 
>> Therefore, for any event with one of trigger bits 1..6 set, trigger bit 8 should also be present (for example, if trigger bit 1 is set, it means that MORA is TRUE, and that there are two sectors with STxTOF, one of which is sector #1: trigger bit 8 is also satisfied for this event).
>> 
>> However, this is not the case for the events I am scrutinizing. I report to you some events showing this issue. I also CC this to Sergey and Ben, so that they can provide further input to the discussion.
>> 
>> 
>> EVENT:
>> Version:        0
>> Run:            56541
>> Event:          858
>> Type:           1  (physics data)
>> ROC:            0
>> CLASS:          14
>> Trgbit:         0x5405        --> bit 1, bit 3, bit 11, bit 13, bit 15. By the way, what are trigger bit 13 and 15? They are not reported in table 2.
>> TIME:           Thu May 21 18:02:01 2144
>> 
>> EVENT:
>> Version:        0
>> Run:            56541
>> Event:          853
>> Type:           1  (physics data)
>> ROC:            0
>> CLASS:          14
>> Trgbit:         0x8c20     --> bit 6, bit 11, bit 12, bit 16. By the way, what is trigger bit 16? This is not reported in table 2.
>> TIME:           Thu May 21 18:02:01 2144
>> 
>> EVENT:
>> Version:        0
>> Run:            56541
>> Event:          947
>> Type:           1  (physics data)
>> ROC:            0
>> CLASS:          14
>> Trgbit:         0x5c15  --> bit 1, bit 3, bit 5, bit 11, bit 12, bit 13, bit 15. By the way, what is trigger bit 15? This is not reported in table 2.
>> TIME:           Thu May 21 18:02:01 2144
>> 
>> 
>> Thanks,
>> Andrea

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