[Hallb-solenoid] Interlock Checkout List P027 Completed

[Wesley Moore]

Not sure what you mean in #1.  For #6, the buttons on the MPS screen were still disabled.  I’ve just activated those, refresh your GUI.  Thought DSG had already checked those in the past, apparently not.  No big deal, you should be able to quickly check them now.

Wesley

> On Oct 7, 2016, at 1:44 PM, Pablo Campero <campero at jlab.org> wrote:
> 
> Dear Ruben,
> 
> Tyler and I completed all tasks Hall B Pre-Power-Up Interlock Checkout Procedure- P027. 
> 
> We noted failures in the following tasks:
> 
> 1. "Verify interlock to prevent over current" 
>         - EPICS would not allows any current set point to be entered, regardless of whether current limit is exceeded.
> 
> 2. "Comparator 4  1st Threshold"
>         -  Because of noise, interlock tripped continuously with a 1st threshold limit of 150 [mV].
>         -  VT10-DAQ (used for comparator 4)  had about 50 [mV] noise with voltage source connected, and 75 [mV] without voltage source connected.
>    
> 3. "Comparator 4  2nd Threshold"
>        -  Because of noise, interlock tripped when the difference between voltage sources was 28 [mV] (It should be about 200 [mV]).
> 
> 4. "Comparator 6  1st Threshold"
>         -  Because of noise, interlock tripped continuously with a 1st threshold limit of 150 [mV].
>         -  VT6-DAQ (used for comparator 6)  had about 50 [mV] noise with voltage source connected.
>    
> 5. "Comparator 6  2nd Threshold"
>        - Because of noise, interlock tripped continuously with a 2nd threshold limit of 200 [mV].
> 
> 6. "Test Danfysik QD  Sum1", "Test Danfysik QD  Sum2" and "Test Danfysik QD  Sum 3"
>        - MPS can not be reset from EPICS.
>        - Had to reset from local MPS control panel . 
>  
> 
> Best Regards
> Pablo Campero
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