[Halld-online] Front-end board data format proposal and adoption

[Elliott Wolin]

Hi,

Attached is Dave A's and Ed's proposal for a consistent data format for 
all JLab front-end modules.  At the last Online meeting we were led to 
believe all JLab modules that get read out over the VME backplane would 
implement this format (FADC25, FADC125, F1TDC, TI, TS, etc).  We are 
proceeding as if this is the case.

Further, we expect to begin reading out detectors this summer, probably 
BCAL and FCAL first (check with Fernando for our crate installation 
schedule).  We would very much like this format to be implemented by the 
time the crates are installed.

FPGA programmers:  please let me know ASAP if you are NOT planning to 
implement this format, or if you won't be able to implement it by the 
time your modules get installed in Hall D and we begin reading them 
out.  We very much do not want to have to deal with multiple formats for 
the same module (e.g. the June 2013 format, the Mar 2015 format, whatever).

Finally, we are developing simulation, readout and analysis code that 
expects this format, so we need to know ASAP if it will change.

Thanks,

-- 

				Sincerely,
					Elliott


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  Those raised in a morally relative or neutral environment will hold
		    no truths to be self-evident.
				

Elliott Wolin
Staff Physicist, Jefferson Lab
12000 Jefferson Ave
Suite 8 MS 12A1
Newport News, VA 23606
757-269-7365

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