[Halld-online] Front-end board data format proposal and adoption

[Fernando J Barbosa]

Hi Elliott,

David already distributed this.

For the latest on schedules, refer to my presentation to the collaboration.

FPGA programmers already know what to do regarding the data format. The 
only part missing is the Hall D final request.

Best regards,
Fernando


On 3/1/2013 3:07 PM, Elliott Wolin wrote:
> Hi,
>
> Attached is Dave A's and Ed's proposal for a consistent data format 
> for all JLab front-end modules.  At the last Online meeting we were 
> led to believe all JLab modules that get read out over the VME 
> backplane would implement this format (FADC25, FADC125, F1TDC, TI, TS, 
> etc).  We are proceeding as if this is the case.
>
> Further, we expect to begin reading out detectors this summer, 
> probably BCAL and FCAL first (check with Fernando for our crate 
> installation schedule).  We would very much like this format to be 
> implemented by the time the crates are installed.
>
> FPGA programmers:  please let me know ASAP if you are NOT planning to 
> implement this format, or if you won't be able to implement it by the 
> time your modules get installed in Hall D and we begin reading them 
> out.  We very much do not want to have to deal with multiple formats 
> for the same module (e.g. the June 2013 format, the Mar 2015 format, 
> whatever).
>
> Finally, we are developing simulation, readout and analysis code that 
> expects this format, so we need to know ASAP if it will change.
>
> Thanks,
>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: barbosa.vcf
Type: text/x-vcard
Size: 276 bytes
Desc: not available
Url : https://mailman.jlab.org/pipermail/halld-online/attachments/20130301/313a16cf/attachment.vcf