[Moller_daq] [EXTERNAL] ADC module timing

[Michael Gericke]

Hello,

The attached summarizes my understanding of the ADC module timing, based 
on simulations and the data we see both in my standalone setup
and what we found when Hanjie and I were looking at the data taken with 
the JLab setup.

The upshot is that there is currently no setup for having the timestamp 
exactly aligned between the TI and the ADC, but that the time difference
can be explained and handled (at least that is my understanding) .

The configuration files should not specify a zero delay after trigger, 
as that currently messes up the data readout. But I think it can be 
specified
to be a small number of samples.

While this email is motivated by the detailed testing at JLab and 
elsewhere and trying to resolving the last remaining issues, the last 
slide illustrates
fairly well what the boards does in integration mode. So I thought it 
would be of interest to people in the DAQ group in general. Also, more eyes
and minds always help.

Thanks,

Michael
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