[Clas12_rich] Test of the mock electronics board

[Valery Kubarovsky]

Hi Marco,

I am not sure how I can check all connectors. We tested the mechanical construction.
All types and PMTs fit into the electronic board.

The extraction of PMTs is a concern. 
As you pointed out there are two versions:

1. Extract PMT from the front. We need a special tools to do. We have to ask our engineers to help us. The possible problem is the stress to the PMT structure during extraction.

2. We can try to remove all tiles. In this case we will meet the problem to install it back.

Regards,
Valery


----- Original Message -----
> From: "mirazita" <Marco.Mirazita at lnf.infn.it>
> To: "Valery Kubarovsky" <vpk at jlab.org>
> Cc: "clas12 rich" <clas12_rich at jlab.org>
> Sent: Friday, June 24, 2016 5:01:04 AM
> Subject: Re: [Clas12_rich] Test of the mock electronics board

> Hi Valery,
> thank you for the pictures.
> There are a couple of things that should be checked.
> The first thing is that all the electric connections are ok.
> The second thing is to see how easy is to remove and put back one pmt
> from the panel.
> We just guessed two possibilities, but we couldn't make tests because we
> don't have the pmt in Frascati.
> One possibility is to remove the pmt from the front, but for this one
> should invent some special tool.
> The second possibility is to remove a full tile, working from the
> ASIC/FPGA board side.
> Marco
> 
> 
> Il 2016-06-23 22:37 Valery Kubarovsky ha scritto:
>> Hi All,
>> 
>> We tested the mock setup with tubes/adapters/ASICS/FPGA boards.
>> Take a look to the pictures.
>> https://userweb.jlab.org/~vpk/RICH12/2016_06_23_Photos_mirror_electronics/
>> Everything fits good from the first view.
>> Regards,
>> Valery
>> 
>> PS. There are several pictures from the mirror test stand as well.
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