[Dsg-hallb_magnets] Solenoid cRIO Filtering

[Brian Eng]

Attached are captures from the live display of different filter setups on the FPGA.

I picked IDCCT1 & VT21 since they were the noisiest.

The screenshot file name indicates what the configuration was: default = no filtering, single notch = only applied to IDCCT1 (60 Hz, 20 Q factor, 10k S/s, allow overflow), notch all = applied to all channels, this reduces bit depth from 24 to 16 (same notch filter settings).

Let me know if there's any questions about the setup. Also,which configuration I should put the FPGA in for normal operations?
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