[Dsg-hallb_magnets] [New Logentry] Solenoid Controlled Ramp

[Probir Ghoshal]

Hi Brian
Please increase the threshold sum of voltages on slices only (in and out lead) not coils or splices between coils by another 25 mV (presently been set to 80 mV) to change to 105 mV. This is on PLC side software limits not on the hardware trip threshold…

Regards
Probir
________________________________
From: Dsg-hallb_magnets <dsg-hallb_magnets-bounces at jlab.org> on behalf of beng--- via Dsg-hallb_magnets <dsg-hallb_magnets at jlab.org>
Sent: Tuesday, October 18, 2022 10:25:02 AM
To: dsg-hallb_magnets at jlab.org <dsg-hallb_magnets at jlab.org>
Subject: [Dsg-hallb_magnets] [New Logentry] Solenoid Controlled Ramp

Solenoid Controlled Ramp<https://logbooks.jlab.org/entry/4062189>

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Lognumber 4062189<https://logbooks.jlab.org/entry/4062189>. Submitted by beng<https://logbooks.jlab.org/user/beng> on Tue, 10/18/2022 - 10:20<https://logbooks.jlab.org/entries?start_date=1666099208&end_date=1666106408&book=DSGLOG&book=HBSOLENOID>.

Logbooks:       DSGLOG<https://logbooks.jlab.org/book/dsglog> HBSOLENOID<https://logbooks.jlab.org/book/hbsolenoid>

According to the PLC it was COMP4 that was the cause of the controlled ramp.

Looking at the VT data nothing stands out as being bad.

Found that the dead-band for the some of the comparators is probably set to low as looking at the archived data doesn't show anything. The threshold for COMP4 is 0.08 and the dead-band is 0.05 as an example.

Various plots are attached.

[https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-mya-interlock.png]
[https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-mya.png]
[https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-interlocks.PNG]
[https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-soft_quench.PNG]
[https://logbooks.jlab.org/files/styles/plentybig/public/2022/10/4062189/2022-10-18-vt.png]
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